Variability-Conscious Circuit Designs for Low-Voltage Memory-Rich Nano-Scale CMOS LSIs

  • Kiyoo Itoh
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)


Low-voltage scaling limitations of nanoscale CMOS LSIs are one of the major problems in the nanoscale era because they cause the evermore-serious power crises with device scaling. The problems stem from two unscalable device parameters: The first is the high value of the lowest necessary threshold voltage Vt (that is, Vt0) of MOSFETs needed to keep the subthreshold leakage low. The second is the variation in Vt (that is, ΔVt), that becomes more prominent in the nanoscale era. The ΔVt caused by the intrinsic random dopant fluctuation is the major source of various ΔVt components. It increases with device scaling and thus intensifies various detrimental effects such as variations in speed and/or the voltage margins of circuits. Due to such inherent features of Vt0 and ΔVt, the operating voltage VDD is facing a 1-V wall in the 65-nm generation, and is expected to rapidly increase with further scaling of bulk MOSFETs, thereby worsening the power crisis. To reduce VDD, the minimum operating voltage Vmin, as determined by Vt0 and ΔVt, must be reduced.

In this talk the Vmin of memory-rich nanoscale CMOS LSIs is investigated in an effort to reduce to below 0.5 V through variability-conscious device and circuit designs. First, Vmin, as a methodology to evaluate the low-voltage potential of MOSFETs, is proposed on the basis of a tolerable speed variation. Second, Vmins of the logic, SRAM, and DRAM blocks are compared, and the SRAM block comprising the six-transistor (6-T) cell turns out to be particularly problematic because it has the highest Vmin. Third, new devices, such as a fully-depleted structure (FD-SOI) and fin-type structure (FinFET) as ΔVt-immune MOSFETs, are investigated to further reduce the Vmins of the above-described blocks. Also investigated are new circuits to reduce Vmin of each block. For example, for the logic block, new dual-Vt0 and dual-VDD dynamic circuits enable the power-delay product to be reduced to 0.09 at a 0.2-V supply owing to gate-source reverse biasing. For the SRAM block, repair techniques, shortening the data line, up-sizing the MOSFETs, control of the common-source line or the word line of the cell, and even the 8-T cell reduce the Vmin. For the DRAM block, if combined with FinFET DRAM cells, a dynamic sense amplifier minimizes the Vt0 and thus Vmin.

Finally, it is concluded that such variability-conscious circuit designs should lead to the achievement of 0.5-V nanoscale LSIs, if relevant devices and fabrication processes are successfully developed.

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Kiyoo Itoh
    • 1
  1. 1.Central Research LaboratoryHitachi, Ltd.KokubunjiJapan

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