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System Level Power Estimation of System-on-Chip Interconnects in Consideration of Transition Activity and Crosstalk

  • Martin Gag
  • Tim Wegner
  • Dirk Timmermann
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)

Abstract

As technology reaches nanoscale order, interconnection systems account for the largest part of power consumption in Systems-on-Chip. Hence, an early and sufficiently accurate power estimation technique is needed for making the right design decisions.

In this paper we present a method for system-level power estimation of interconnection fabrics in Systems-on-Chip. Estimations with simple average assumptions regarding the data stream are compared against estimations considering bit level statistics in order to include low level effects like activity factors and crosstalk capacitances. By examining different data patterns and traces of a video decoding system as a realistic example, we found that the data dependent effects are not negligible influences on power consumption in the interconnection system of nanoscale chips. Due to the use of statistical data there is no degradation of simulation speed in our approach.

Keywords

Power Estimation Very Large Scale Integration Interconnection System Coupling Capacitance Word Width 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Martin Gag
    • 1
  • Tim Wegner
    • 1
  • Dirk Timmermann
    • 1
  1. 1.Institute of Applied Microelectronics and Computer EngineeringUniversity of RostockGermany

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