An All-Digital Phase-Locked Loop with High Resolution for Local On-Chip Clock Synthesis
In this paper an All-Digital Phase-Locked Loop (ADPLL) with a high resolution and a wide frequency range for local on-chip clock generation is described. The proposed ADPLL has an operating range from 250MHz to 1.3GHz and a resolution of 25 ps. In contrast to other designs, the Digitally Controlled Oscillator (DCO) combines three different development approaches to achieve the desired performance. The ADPLL provides four different algorithms to control the DCO. Depending on the selected algorithm and the desired frequency, the lock-in time varies between 54 to more than hundreds reference cycles. The output of the synthesized clock is directly connected to a Low Voltage Differential Signaling (LVDS) interface to provide a high frequency LVDS clock. Before their VHDL implementation, all components were simulated using an event driven Matlab model. This proposed ADPLL uses standard cell library elements only and is implemented in an IHP 0.25 μm BiCMOS process. The overall power dissipation is less than 50mW (@ 800MHz) with a 2.5V power supply. Due to its VHDL description the design can be ported to other processes in short development time.
KeywordsAll-Digital Phase-Locked Loop ADPLL Clock Generator Event driven Matlab Model LVDS PID Controller
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