Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

  • Marco Lanuzza
  • Raffaele De Rose
  • Fabio Frustaci
  • Stefania Perri
  • Pasquale Corsonello
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)


Process variations cause unpredictability in speed and power characteristics of nanometer CMOS circuits impacting the timing and energy yields. In this paper, transistor reordering and dual-Vth techniques are evaluated regarding their efficiency in mitigating the impact of process variations on a set of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 1.62X and 1.99X times, respectively. The yield optimized flip-flop circuits are also comparatively analyzed to identify the best topologies.


Monte Carlo Process Variation Setup Time Input Buffer Dynamic Power Consumption 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Marco Lanuzza
    • 1
  • Raffaele De Rose
    • 1
  • Fabio Frustaci
    • 1
  • Stefania Perri
    • 1
  • Pasquale Corsonello
    • 1
  1. 1.Departement of Electronics, Computer Science and SystemsUniversity of CalabriaRende (CS)Italy

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