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Logic Architecture and VDD Selection for Reducing the Impact of Intra-die Random VT Variations on Timing

  • Bahman Kheradmand-Boroujeni
  • Christian Piguet
  • Yusuf Leblebici
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)

Abstract

We show that in logic circuits working at supply voltage (VDD) below nominal value, proper selection of logic architecture and VDD together can reduce the impact of device-to-device random process variations (PV) on timing. First we show that σ/μ of transistor current and delay strongly depend on VDD. Then we compare the PV sensitivity of Low-Power Slow (LP-S) and High-Power Fast (HP-F) architectures. The results propose the idea that for a given technology, equal power budget and delay, LP-S circuits working at higher VDD are about 1.8X less PV sensitive compare to HP-F circuits working at lower VDD.

Keywords

Low-Voltage Low-Power Process Variation Random Variations Statistical Variability Flip-Flop Digital VLSI 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Bahman Kheradmand-Boroujeni
    • 1
    • 2
  • Christian Piguet
    • 1
  • Yusuf Leblebici
    • 2
  1. 1.Integrated and Wireless SystemsCentre Suisse d’Electronique et de Microtechnique (CSEM)NeuchâtelSwitzerland
  2. 2.Microelectronic Systems LaboratoryEcole Polytechnique Fédérale de Lausanne (EPFL)LausanneSwitzerland

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