Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip

  • Alberto Garcia-Ortiz
  • Leandro S. Indrusiak
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)


Low-power coding represents an important technique to reduce consumption in modern interconnect architectures. In the case of Network-on-Chip, and specially if they include virtual channels, the coding techniques require to be effective (large reduction of transition activity) and extremely efficient (reduced hardware resources). This work proposes a coding template called PM with those characteristics. Moreover, it shows with a detailed theoretical analysis and a number of experiments the good characteristics of the approach. Some relevant theoretical results on Exact Probability Coding are also developed in the paper.


Processing Element Network Interface Virtual Channel Dynamic Power Consumption Probability Coder 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Benini, L., Macii, A., Macii, E., Poncino, M., Scarsi, R.: Architectures and synthesis algorithms for power-efficient bus interfaces. IEEE Trans. on CAD 19, 969–980 (2000)CrossRefGoogle Scholar
  2. 2.
    de Micheli, G., Benini, L.: Networks on chip: A new paradigm for systems on chip design. In: DATE 2002, Washington, DC, USA, p. 418. IEEE Computer Society, Los Alamitos (2002)Google Scholar
  3. 3.
    Ganguly, A., Pande, P., Belzer, B.: Crosstalk-Aware Channel Coding Schemes for Energy Efficient and Reliable NOC Interconnects. IEEE Trans. on VLSI 17(11), 1626–1639 (2009)CrossRefGoogle Scholar
  4. 4.
    García Ortiz, A., Indrusiak, L.S., Murgan, T., Glesner, M.: Low-Power Coding for Networks-on-Chip with Virtual Channels. Journal of Low Power Electronics (JOLPE) 1(4), 77–84 (2009)CrossRefGoogle Scholar
  5. 5.
    Lee, K., Lee, S., Yoo, H.: Low-Power Network-on-Chip for High-Performance SoC Design. IEEE Trans. on VLSI 14(02), 148–160 (2006)CrossRefGoogle Scholar
  6. 6.
    Mullins, R.: Minimising dynamic power consumption in on-chip networks. In: Procs of the Intl. Symp. on System-on-Chip, Tampere, Finland (November 2006)Google Scholar
  7. 7.
    Palma, J.-C., Indrusiak, L., Moraes, F., García Ortiz, A., Glesner, M., Reis, R.: Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. In: Vounckx, J., Azémard, N., Maurine, P. (eds.) PATMOS 2006. LNCS, vol. 4148, pp. 603–613. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  8. 8.
    Ramprasad, S., Shanbhag, N., Hajj, I.: A coding framework for low-power address and data buses. IEEE Trans. on VLSI Systems 7, 212–221 (1999)CrossRefGoogle Scholar
  9. 9.
    Sotiriadis, P.P., Tarokh, V., Chandrakasan, A.P.: Energy reduction in VLSI computation modules: an information-theoretic approach. IEEE Transactions on Information Theory 49(4), 790–808 (2003)MathSciNetCrossRefzbMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Alberto Garcia-Ortiz
    • 1
  • Leandro S. Indrusiak
    • 2
  1. 1.Institute for Theoretical Electrical Eng. and Microelectronics (ITEM)University of BremenBremenGermany
  2. 2.Dept. of Computer Science - Real-Time Systems Group (RTS)University of YorkYorkUK

Personalised recommendations