Optimizing and Comparing CMOS Implementations of the C-Element in 65nm Technology: Self-Timed Ring Case

  • Oussama Elissati
  • Eslam Yahya
  • Sébastien Rieubon
  • Laurent Fesquet
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)


Self-timed rings are a promising approach for designing high-speed serial links or clock generators. This study focuses on the ring stage components – a C-element and an inverter - and compares the performances of different implementations of this component in terms of speed, power consumption and phase noise. We also proposed a new self-timed ring stage - only composed by a C-element with complementary outputs - which allows us to increase the maximum speed of 25% and reduce the power consumption of 60% at the maximum frequency. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics.


Phase Noise Voltage Control Oscillator Flicker Noise Ring Stage Electrical Simulation 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Oussama Elissati
    • 1
    • 2
  • Eslam Yahya
    • 1
    • 3
  • Sébastien Rieubon
    • 2
  • Laurent Fesquet
    • 1
  1. 1.TIMA LaboratoryGrenobleFrance
  2. 2.ST-EricssonGrenobleFrance
  3. 3.Banha High Institute of TechnologyBanhaEgypt

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