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Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations

  • Mohsen Raji
  • Alireza Tajary
  • Behnam Ghavami
  • Hossein Pedram
  • Hamid R. Zarandi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)

Abstract

Increasing levels of process variability in deep sub micron era has become a critical concern for performance and power constraint designs. This paper introduces a framework for the statistical leakage power minimization of template-based asynchronous circuits considering process variation. We propose a statistical Dual-Vt assignment of asynchronous circuits that considers both the variability in performance and leakage power consumption of a circuit. The utilized circuit model is an extended Timed Petri-Net named Variant-Timed Petri-Net which captures the dynamic behavior of the circuit with statistical delay and leakage power values. We applied a genetic algorithm that uses a 2-dimensional graph to calculate the fitness to each threshold voltage assignment. Experimental results show that using this statistically aware optimization, leakage power can be reduced by 40.5% and 54.4% for the mean and the variance values.

Keywords

Monte Carlo Threshold Voltage Power Optimization Flow Leakage Power Asynchronous Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Mohsen Raji
    • 1
  • Alireza Tajary
    • 1
  • Behnam Ghavami
    • 1
  • Hossein Pedram
    • 1
  • Hamid R. Zarandi
    • 1
  1. 1.Department of Computer Engineering and Information TechnologyAmirkabir University of Technology (Tehran Polytechnic)TehranI.R. of Iran

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