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Abstract

Portable digital systems tend to be not just low power but power efficient as they are powered by low batteries or energy harvesters. Energy harvesting systems tend to provide nondeterministic, rather than stable, power over time. Existing memory systems use delay elements to cope with the problems under different Vdds. However, this introduces huge penalties on performance, as the delay elements need to follow the worst case timing assumption under the worst environment. In this paper, the latency mismatch between memory cells and the corresponding controller using typical delay elements is investigated and found to be highly variable for different Vdd values. A Speed Independent (SI) SRAM memory is then developed which can help avoid such mismatch problems. It can also be used to replace typical delay lines for use in bundled-data memory banks. A 1Kb SI memory bank is implemented based on this method and analysed in terms of the latency and power consumption.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Abdullah Baz
    • 1
  • Delong Shang
    • 1
  • Fei Xia
    • 1
  • Alex Yakovlev
    • 1
  1. 1.Microelectronic System Design Group, School of EECENewcastle UniversityNewcastle upon TyneEngland, UK

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