On Line Power Optimization of Data Flow Multi-core Architecture Based on Vdd-Hopping for Local DVFS

  • Pascal Vivet
  • Edith Beigne
  • Hugo Lebreton
  • Nacer-Eddine Zergainoh
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6448)


With growing integration, power consumption is becoming a major issue for multi-core chips. At system level, per-core DVFS is expected to save substantial energy provided an adapted control. In this paper we propose a local on-line optimization technique to reduce energy in data-flow architecture, thanks to a Local Power Manager (LPM) using Vdd-Hopping for efficient local DVFS. The proposed control is a hybrid global and local scheme which respects throughput and latency constraints. The approach has been fully validated on a real MIMO Telecom application using a SystemC platform instrumented with power estimates. Local DVFS brings 45% power reduction compared to idle mode. When local on-line optimization benefit from computation time variations, 30% extra energy savings can be achieved.


Low Power DVFS VDD-Hopping 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Pascal Vivet
    • 1
  • Edith Beigne
    • 1
  • Hugo Lebreton
    • 1
  • Nacer-Eddine Zergainoh
    • 2
  1. 1.CEA-Leti, MinatecGrenobleFrance
  2. 2.TIMAGrenobleFrance

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