Abstract
BCH(Bose-Chaudhuri-Hoquenbhem) code, a type of block codes-cyclic codes, has very strong error-correcting ability which is vital for performing the error protection on the memory system. BCH code has many kinds of dual algorithms, PGZ(Pererson-Gorenstein-Zierler) algorithm out of them is advantageous in view of correcting the errors through the simple calculation in t value. However, this is problematic when this becomes 0 (divided by zero) in case ν ≠ t. In this paper, the circuit would be simplified by suggesting the multi-mode hardware architecture in preparation that v were 0~3. First, production cost would be less thanks to the smaller number of gates. Second, lessening power consumption could lengthen the recharging period. The very low cost and simple datapath make our design a good choice in small-footprint SoC(System on Chip) as ECC(Error Correction Code/Circuit) in memory system.
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Seo, H., Han, S., Heo, Y., Cho, T. (2010). A Very Low Cost BCH Decoder for High Immunity of On-Chip Memories. In: Kim, Th., Yau, S.S., Gervasi, O., Kang, BH., Stoica, A., Ślęzak, D. (eds) Grid and Distributed Computing, Control and Automation. GDC CA 2010 2010. Communications in Computer and Information Science, vol 121. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17625-8_24
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DOI: https://doi.org/10.1007/978-3-642-17625-8_24
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-17624-1
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