FEDTIC: A Security Design for Embedded Systems with Insecure External Memory

  • Mei Hong
  • Hui Guo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6485)


This paper presents a security design for embedded systems that have a secure on-chip computing environment and an insecure off-chip memory. The design protects the confidentiality and integrity of data at a low cost on performance and memory consumption. We implemented the design based on the SimpleScalar simulation software. Our simulation on a set of benchmarks shows that very little overhead is incurred for on-chip memory, and the average overheads on performance and off-chip memory, are only 7.6% and 6.25%, respectively.


Embed System External Memory Cache Size Cache Line Performance Overhead 
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  1. 1.
    Gelbart, O., Leontie, E., Narahari, B., Simha, R.: A compiler-hardware approach to software protection for embedded systems. Computers and Electrical Engineering, 315–328 (2009)Google Scholar
  2. 2.
    Ravi, S., Raghunathan, A., Chakradhar, S.: Tamper resistance mechanisms for secure embedded systems. In: 17th International Conference on VLSI Design (2004)Google Scholar
  3. 3.
    Best, R.M.: Prevent software piracy with crypto-microprocessors. In: IEEE Computer Society International Conference (1980)Google Scholar
  4. 4.
    Dallas Semiconductor (2008),
  5. 5.
    Blum, M., Evans, W., Gemmell, P., Kannan, S., Naor, M.: Checking the correctness of memories. In: 32nd Annual Symposium on Foundations of Computer Science (1991)Google Scholar
  6. 6.
    Lie, D., Chandramohan, T., Mitchell, M., Lincoln, P., Boneh, D., Mitchell, J., Horowitz, M.: Architectural support for copy and tamper resistant software. In: 9th Internatinal Conference Architectural Support for Programming Languages and Operating Systems, ASPLOS-IX (2000)Google Scholar
  7. 7.
    Lie, D., Thekkath, C.A., Horowitz, M.: Implementing an untrusted operating system on trusted hardware. In: 19th ACM Symposium on Operating System Principles (2003)Google Scholar
  8. 8.
    Suh, G.E., Clarke, D., Gasend, B., van Dijk, M., Devadas, S.: AEGIS:architecure for tamper-evident and tamper-resistant processing. In: International Conference on SuperComputing (2003)Google Scholar
  9. 9.
    Suh, G.E., óDonnell, C.W., Sachdev, I., Devadas, S.: Design and implementation of the AEGIS single-chip secure processor using physical random functions. In: 32nd Interntional Symposium on Computer Architecture, ISCA (2005)Google Scholar
  10. 10.
    Suh, G.E., óDonnell, C.W., Sachdev, I., Devadas, S.: AEGIS: A single-chip secure processor. IEEE Design and Test of Computers, 467–477 (2007)Google Scholar
  11. 11.
    Duc, G., Keryell, R.: Cryptopage: An efficient secure architecture with memory encryption, integrity and information leakage protection. In: 22nd Annual Computer Security Applications Conference, ACSAC 2006 (2006)Google Scholar
  12. 12.
    Elbaz, R., Champagne, D., Lee, R.B., Torres, L.: Tec-tree: a low-cost, parallelizable tree for efficient defense against memory replay attacks. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 289–302. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  13. 13.
    Bellare, M., Namprempre, C.: Authenticated encryption: Relations among notions and analysis of the generic composition paradigm. Journal of Cryptology 21(4), 469–491 (2008)MathSciNetCrossRefzbMATHGoogle Scholar
  14. 14.
    Rogaway, P., Bellare, M., Black, J., Krovetz, T.: OCB: a block-cipher mode of operation for efficient authenticated encryption. In: ACM conference on Computer and communications Security (2001)Google Scholar
  15. 15.
    Austin, T.M., Burger, D.B.: The simplescalar tool set, version 3.0. Technical report, University of Wisconsin-madision (1997)Google Scholar
  16. 16.
    Helion Technology Datasheet: high performance AES (Rijndael) cores for Xilinx FPGAs (2008),
  17. 17.
    Henning, J.L.: SPEC CPU 2000: Measuing CPU performance in the new millennium. IEEE Computers (2000)Google Scholar
  18. 18.
    Guthaus, M.R., Ringenberg, J.S.: Mibench: a free, commercially representiative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization (2001)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Mei Hong
    • 1
  • Hui Guo
    • 1
  1. 1.School of Computer Science and EngineeringThe University of New South WalesSydneyAustralia

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