Abstract
This paper presents a Pairing Crypto Processor (PCP) over Barreto-Naehrig curves (BN curves). The proposed architecture is specifically designed for field programmable gate array (FPGA) platforms. The design of PCP utilizes the efficient implementation of the underlying finite field primitives. The techniques proposed maximize the utilization of in-built features of an FPGA device which significantly improves the performance of the primitives.
Extensive parallelism techniques have been proposed to realize a PCP which requires lesser clock cycles than the existing designs. The proposed design is the first reported result on an FPGA platform for 128-bit security. The PCP provides flexibility to choose the curve parameters for pairing computations.
The cryptoprocessor needs 1730 k, 1206 k, and 821 k cycles for the computation of Tate, ate, and R-ate pairings, respectively. On a Virtex-4 FPGA device it consumes 52 kSlices at 50MHz and computes the Tate, ate, and R-ate pairings in 34.6 ms, 24.2 ms, and 16.4 ms, respectively, which is comparable to known CMOS implementations.
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Ghosh, S., Mukhopadhyay, D., Roychowdhury, D. (2010). High Speed Flexible Pairing Cryptoprocessor on FPGA Platform. In: Joye, M., Miyaji, A., Otsuka, A. (eds) Pairing-Based Cryptography - Pairing 2010. Pairing 2010. Lecture Notes in Computer Science, vol 6487. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17455-1_28
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