Abstract
In Chap. 5 we described an application specific integrated circuit consisting of programmable polymorphic nodes that resembled the CGP representation. A search algorithm, running on an external personal computer, was used to evolve configurations as well as interconnection of the nodes. In this chapter we describe how complete CGP system (i.e., the array of programmable nodes and search algorithm) can be implemented on a single chip. The implementation is carried out using a field-programmable gate array (FPGA) – a reconfigurable chip which provides a high performance and flexibility in computing for a moderate cost. In comparison with CGP running on a personal computer, the main advantages of the FPGA implementation are a significant speed-up that can be obtained for many applications and a possibility to build small low-power adaptive embedded systems. This chapter introduces the complete FPGA implementations of CGP which can typically be used to accelerate combinational circuit evolution (see Chap. 5) and image filter evolution (see Chap. 6).
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Sekanina, L., Vasicek, Z. (2011). CGP Acceleration Using Field-Programmable Gate Arrays. In: Miller, J. (eds) Cartesian Genetic Programming. Natural Computing Series. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17310-3_7
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DOI: https://doi.org/10.1007/978-3-642-17310-3_7
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