On the Design of a Hardware-Software Architecture for Acceleration of SVM’s Training Phase

  • Lázaro Bustio-Martínez
  • René Cumplido
  • José Hernández-Palancar
  • Claudia Feregrino-Uribe
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6256)


Support Vector Machines (SVM) is a new family of Machine Learning techniques that have been used in many areas showing remarkable results. Since training SVM scales quadratically (or worse) according of data size, it is worth to explore novel implementation approaches to speed up the execution of this type of algorithms. In this paper, a hardware-software architecture to accelerate the SVM training phase is proposed. The algorithm selected to implement the architecture is the Sequential Minimal Optimization (SMO) algorithm, which was partitioned so a General Purpose Processor (GPP) executes operations and control flow while the coprocessor executes tasks than can be performed in parallel. Experiments demonstrate that the proposed architecture can speed up SVM training phase 178.7 times compared against a software-only implementation of this algorithm.


SVM SMO FPGA Parallel hardware-software architectures 


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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Lázaro Bustio-Martínez
    • 1
    • 2
  • René Cumplido
    • 2
  • José Hernández-Palancar
    • 1
  • Claudia Feregrino-Uribe
    • 2
  1. 1.Advanced Technologies Application CenterHavanaCuba
  2. 2.National Institute for Astrophysics, Optics and ElectronicTonantzintlaMéxico

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