Abstract
This paper reports an AES (Advances Encryption Standard) hardware architecture based on Programmable Cellular Automata (PCA) operated with a program. Verilog code has been designed for PCA and associated hardware modules to realize the AES functions. The PCA replaces the irregular logic circuit necessary for hardwired implementation of AES. The design has been simulated on Xilinx platform using ISE simulator.
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Maiti, N.S., Ghosh, S., Shikdar, B.K., Pal Chaudhuri, P. (2010). Programmable Cellular Automata (PCA) Based Advanced Encryption Standard (AES) Hardware Architecture. In: Bandini, S., Manzoni, S., Umeo, H., Vizzari, G. (eds) Cellular Automata. ACRI 2010. Lecture Notes in Computer Science, vol 6350. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15979-4_29
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DOI: https://doi.org/10.1007/978-3-642-15979-4_29
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-15978-7
Online ISBN: 978-3-642-15979-4
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