Abstract
Ultrathin body silicon on insulator technology has acquired during the last few years a significant maturity. Since it offers breakthroughs in terms of electrostatic control and variability, this technology is today a serious alternative to bulk for the coming technology generations. This technology is indeed likely to be scaled down to the 10 nm range. In addition, several performance booster options can be efficiently implemented to reach very high transistor performances. Furthermore, gate stacks allowing the design of low, medium and high threshold voltage transistors are identified and their integration is demonstrated. Finally, the use of an ultrathin buried oxide together with an implanted back-plane brings additional flexibility in terms of threshold voltage adjustment, and ensures the efficiency of conventional power management techniques based on back-biasing, even in very aggressively scaled devices.
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References
International Technology Roadmap for Semiconductors (2009) Edition
Suzuki, K., Tanaka, T., Tosaka, Y., et al.: Scaling theory for double-gate SOI MOSFETs. IEEE Trans. Electron. Devices 40, 2326–2329 (1993)
Buj-Durfournet, C., Andrieu, F., Faynot, O., et al.: Counter-doping as a solution for multi threshold voltage on FDSOI MOSFETs with a single TiN/HfO2 gate stack. In: Proceedings of the Solid State Device and Materials (SSDM) Conference (2009)
Weber, O., Faynot, O., Andrieu, F., et al.: High immunity to threshold voltage variability in undoped ultra-thin FDSOI MOSFETs and its physical understanding. In: Proceedings of the International Electron Devices Meeting (IEDM) Technology Digest, pp. 641–644 (2008)
Fenouillet-Beranger, C., Denorme, S., Perreau, P., et al.: FDSOI devices with thin BOX and ground plane integration for 32 nm node and below. In: Proceedings of the Solid-State Device Research Conference (ESSDERC), pp. 206–209 (2008)
Andrieu, F., Weber, O., Baudot, S., et al.: Fully depleted silicon-on-insulator with back bias and strain for low power and high performance applications. In: Proceedings of the International Conference on IC Design and Technology (ICICDT) (2010)
Andrieu, F., Weber, O., Mazurier, J., et al.: Low leakage and low variability ultra-thin body and buried oxide (UT2B) SOI technology for 20 nm low power CMOS and beyond. In: Proceedings of the International Symposium on VLSI Technology (2010)
Barral, V., Poiroux, T., Andrieu, F., et al.: Strained FDSOI CMOS technology scalability down to 2.5 nm film thickness and 18 nm gate length with a TiN/HfO2 gate stack. In: Proceedings of the International Electron Device Meeting (IEDM) Technology Digest, pp. 61–64 (2007)
Scheiblin, P., Weber, O., Andrieu, F., et al.: Ultra-thin body and BOX SOI roadmap for low power and low VT-variability MOSFETs. In: Proceedings of the EUROSOI Conference (2008)
Vandooren, A., Thean, A.V.Y., Du, Y., et al.: Mixed-signal performance of sub-100 nm fully-depleted SOI devices with metal gate, high-K (HfO2) dielectric and elevated source/drain extensions. In: Proceedings of the International Electron Device Meeting (IEDM) Technology Digest, pp. 978–981 (2003)
Cheng, K., Khakifirooz, A., Kukarny, P., et al.: Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In: Proceedings of the International Electron Device Meeting (IEDM) Technology Digest, pp. 49–52 (2009)
Fenouillet-Beranger, C., Thomas, O., Perreau, P., et al.: Efficient multi-VT FDSOI technology with UTBOX for low power circuit design. In: Proceedings of the International Symposium on VLSI Technology (2010)
Fenouillet-Beranger, C., Pham Nguyen, L., Perreau, P., et al.: Ultra compact FDSOI transistors (including strain and orientation) processing and performance. ECS Trans. (2009)
Baudot, S., Andrieu, F., Faynot, O., et al.: Electrical and diffraction characterization of short and narrow MOSFETs on Fully Depleted strained Silicon-On-Insulator (sSOI). Solid State Electron. 54, 861–869 (2010)
Andrieu, F., Fenouillet-Béranger, C., Weber, O., et al.: Ultrathin body and BOX SOI and sSOI for low power application at the 22 nm technology node and below. In: Proceedings of the Solid State Device and Material (SSDM) Conference (2009)
Baudot, S., Andrieu, F., Weber, O., et al.: Fully-Depleted Strained Silicon-On-Insulator p-MOSFETs with recessed and embedded silicon-germanium source/drain (to be published)
Andrieu, F., Ernst, T., Faynot, O., et al.: Co-integrated dual strained channel on fully depleted sSDOI CMOSFETs with HfO2/TiN gate stack down to 15 nm gate length. In: Proceedings of the IEEE International SOI Conference, pp. 223–225 (2005)
Mizuno, T., Sugiyama, N., Tezuka, T., et al.: (110)-surface strained-SOI CMOS devices. IEEE Trans. Electron. Devices 52, 367–374 (2005)
Signamarcheix, T., Andrieu, F., Biasse, B., et al.: Fully depleted silicon on insulator MOSFETs on (110) surface for hybrid orientation technologies. In: Proceedings of EUROSOI Conference (2010)
Acknowledgments
This work was partially carried out in the frame of the LETI/ST/IBM joint program. It has been partly funded by the French Ministry of Industry, Economy and Finance through the MEDEA Decisif project and by the OSEO Nanosmart program. The authors thank the LETI facilities for device processing.
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Poiroux, T. et al. (2011). Ultrathin Body Silicon on Insulator Transistors for 22 nm Node and Beyond. In: Nazarov, A., Colinge, JP., Balestra, F., Raskin, JP., Gamiz, F., Lysenko, V. (eds) Semiconductor-On-Insulator Materials for Nanoelectronics Applications. Engineering Materials. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15868-1_8
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DOI: https://doi.org/10.1007/978-3-642-15868-1_8
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