Ultrathin Body Silicon on Insulator Transistors for 22 nm Node and Beyond

  • T. PoirouxEmail author
  • F. Andrieu
  • O. Weber
  • C. Fenouillet-Béranger
  • C. Buj-Dufournet
  • P. Perreau
  • L. Tosti
  • L. Brevard
  • O. Faynot
Part of the Engineering Materials book series (ENG.MAT.)


Ultrathin body silicon on insulator technology has acquired during the last few years a significant maturity. Since it offers breakthroughs in terms of electrostatic control and variability, this technology is today a serious alternative to bulk for the coming technology generations. This technology is indeed likely to be scaled down to the 10 nm range. In addition, several performance booster options can be efficiently implemented to reach very high transistor performances. Furthermore, gate stacks allowing the design of low, medium and high threshold voltage transistors are identified and their integration is demonstrated. Finally, the use of an ultrathin buried oxide together with an implanted back-plane brings additional flexibility in terms of threshold voltage adjustment, and ensures the efficiency of conventional power management techniques based on back-biasing, even in very aggressively scaled devices.


Threshold Voltage Metal Gate Drain Induce Barrier Lowering Static Noise Margin Line Edge Roughness 
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This work was partially carried out in the frame of the LETI/ST/IBM joint program. It has been partly funded by the French Ministry of Industry, Economy and Finance through the MEDEA Decisif project and by the OSEO Nanosmart program. The authors thank the LETI facilities for device processing.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • T. Poiroux
    • 1
    Email author
  • F. Andrieu
    • 1
  • O. Weber
    • 1
  • C. Fenouillet-Béranger
    • 1
  • C. Buj-Dufournet
    • 1
  • P. Perreau
    • 1
  • L. Tosti
    • 1
  • L. Brevard
    • 1
  • O. Faynot
    • 1
  1. 1.CEA-LETI/MinatecGrenoble Cedex 9France

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