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SOI CMOS: A Mature and Still Improving Technology for RF Applications

  • Jean-Pierre RaskinEmail author
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Part of the Engineering Materials book series (ENG.MAT.)

Abstract

This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency (reaching cut-off frequencies close to 500 GHz for nMOSFETs) and for harsh environments (high temperature, radiation) commercial applications. For RF and system-on-chip applications, SOI also presents the major advantage of providing high resistivity substrate capabilities, leading to substantially reduced substrate losses. Substrate resistivity values higher than 1 kΩ cm can easily be achieved and high resistivity silicon is commonly foreseen as a promising substrate for radio frequency integrated circuits and mixed signal applications. In this chapter, based on several experimental and simulation results, the interest, limitations but also possible future improvements of the SOI MOS technology are presented.

Keywords

Schottky Barrier Gate Length High Frequency Characteristic Fringe Capacitance Dopant Segregation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

I would like to thank all the Ph.D. students, senior researchers, and professors who have actively participated to the simulation and experimental results presented in this chapter: Mr. M. Emam, Mr. C. Roda Neve, Mr. R. Ambroise, Dr. M. El Kaamouchi, Dr. M. Si Moussa, Dr. R. Valentin, Dr. D. Bol, Dr. V. Kilchytska, Dr. A. Kranti, Dr. D. Lederer, Dr. C. Urban, Dr. Qing-Tai Zhao, Dr. O. Moldovan, Prof. B. Iniguez, Prof. D. Flandre, Prof. F. Danneville, Prof. E. Dubois and Prof. S. Mantl. I would like to also thank Mr. P. Simon (Welcome) for performing most of the RF measurements, the UCL clean rooms team (Winfab), as well as Dr. Jurczak Malgorzata’s group and Dr. S. Decoutere’s group (especially Dr. B. Parvais, Dr. M. Dehan, Dr. A. Mercha, Dr. Subramanian Vaidy), IMEC, Leuven, Belgium, for providing FinFETs. This research has been financially supported by the European Networks of Excellence SINANO, NANOSIL and EuroSOI+.

References

  1. 1.
    Moore, G.E.: Cramming more components onto integrated circuits. Electronics 38, 114–117 (1965)Google Scholar
  2. 2.
    Dennard, R.H., Gaensslen, F.H., Hwa-Nien, Yu., Rideout, V.L., Bassous, E., Leblanc, A.R.: Design of ion-implanted MOSFET’s with very small physical dimensions. IEEE J. Solid State Circuits 9, 256–268 (1974)CrossRefGoogle Scholar
  3. 3.
    Lee, S., Jagannathan, B., Narasimha, S., Chou, A., Zamdmerm N., Johnson, J., Williams, R., Wagner, L., Kim, J., Plouchart, J.-O., Pekarik, J., Springer, S., Freeman, G.: Record RF performance of 45-nm SOI CMOS technology. IEEE Int. Electron Devices Meeting IEDM, pp. 255–258 (2007)Google Scholar
  4. 4.
    Sakurai, T., Matsuzawa, A., Douseki, T.: Fully-depleted SOI CMOS circuits and technology for ultralow-power applications. Springer XV ISBN:978-0-387-29217-5 (2006)Google Scholar
  5. 5.
    Raskin, J.-P., Viviani, A., Flandre, D., Colinge, J.-P.: Substrate crosstalk reduction using SOI technology. IEEE Trans. Electron Devices 44, 2252–2261 (1997)CrossRefGoogle Scholar
  6. 6.
    Cooke, H.F.: Microwave transistors: theory and design. Proc. IEEE 59, 1163–1181 (1971)CrossRefGoogle Scholar
  7. 7.
    Mead, C.A.: Schottky barrier gate field effect transistor. Proc. IEEE 59, 307–308 (1966)CrossRefGoogle Scholar
  8. 8.
    Baechtold, W., Daetwyler, K., Forster, T., Mohr, T.O., Walter, W., Wolf, P.: Si and GaAs 0.5 μm gate Schottky-barrier field-effect transistors. Electron Lett. 9, 232–234 (1973)CrossRefGoogle Scholar
  9. 9.
    Mimura, T., Hiyamizu, S., Fujii, T., Nanbu, K.: A new field-effect transistor with selectively doped GaAs/n-AlxGa1-xAs heterojunctions. Jpn. J. Appl. Phys. 19, L225–L227 (1980)CrossRefGoogle Scholar
  10. 10.
    Smith, P.M., Liu, S.-M.J., Kao, M.-Y., Ho, P., Wang, S.C., Duh, K.H.G., Fu, S.T., Chao, P.C.: W-band high efficiency InP-based power HEMT with 600 GHz fmax. IEEE Microw. Guid. Wave Lett. 5, 230–232 (1995)CrossRefGoogle Scholar
  11. 11.
    Rodwell, M.J.W., Urteaga, M., Mathew, T., Scott, D., Mensa, D., Lee, Q., Guthrie, J., Betser, Y., Martin, S.C., Smith, R.P., Jaganathan, S., Krishnan, S., Long, S.I., Pullela, R., Agarwal, B., Bhattacharya, U., Samoska, L., Dahlstrom, M.: Submicron scaling of HBTs. IEEE Trans. Electron Dev. 48, 2606–2624 (2001)CrossRefGoogle Scholar
  12. 12.
    Lai, R., Mei, X.B., Deal, W.R., Yoshida, W., Kim, Y.M., Liu, P.H., Lee, J., Uyeda, J., Radisic, V., Lange, M., Gaier, T., Samoska, L., Fung, A.: Sub 50 nm InP HEMT device with Fmax greater than 1 THz. IEEE Int. Electron Devices Meet., pp. 609–611 (2007)Google Scholar
  13. 13.
    Momose, H.S., Morifuji, E., Yoshitomi, T., Ohguro, T., Saito, I., Morimoto, T., Katsumata, Y., Iwai, H.: High-frequency AC characteristics of 1.5 nm gate oxide MOSFETs. IEEE Int. Electron Devices Meet., pp. 105–108 (1996)Google Scholar
  14. 14.
    International Technology Roadmap for Semiconductors. http://www.itrs.net/Common/2006ITRS/Home2006.html
  15. 15.
    Dambrine, G., Raynaud, C., Lederer, D., Dehan, M., Rozeaux, O., Vanmackelberg, M., Danneville, F., Lepilliet, S., Raskin, J.P.: What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? IEEE Electron Device Lett. 24, 189–191 (2003)CrossRefGoogle Scholar
  16. 16.
    Pailloncy, G., Raynaud, C., Vanmackelberg, M., Danneville, F., Lepilliet, S., Raskin, J.-P., Dambrine, G.: Impact of down scaling on high frequency noise performance of bulk and SOI MOSFETs. IEEE Trans. Electron Devices 51, 1605–1612 (2004)CrossRefGoogle Scholar
  17. 17.
    Kilchytska, V., Nève, A., Vancaillie, L., Levacq, D., Adriaensen, S., van Meer, H., De Meyer, K., Raynaud, C., Dehan, M., Raskin, J.-P., Flandre, D.: Influence of device engineering on the analog and RF performances of SOI MOSFETs. IEEE Trans. Electron Devices 50, 577–588 (2003)CrossRefGoogle Scholar
  18. 18.
    Vanmackelberg, M., Raynaud, C., Faynot, O., Pelloie, J.-L., Tabone, C., Grouillet, A., Martin, F., Dambrine, G., Picheta, L., Mackowiak, E., Llinares, P., Sevenhans, J., Compagne, E., Fletcher, G., Flandre, D., Dessard, V., Vanhoenacker, D., Raskin, J.-P.: 0.25 μm fully-depleted SOI MOSFET’s for RF mixed analog-digital circuits, including a comparison with partially-depleted devices for high frequency noise parameters. Solid State Electron. 46, 379–386 (2002)CrossRefGoogle Scholar
  19. 19.
    Burignat, S., Flandre, D., Kilchytska, V., Andrieux, F., Faynot, O., Raskin, J.-P.: Substrate impact on sub-32 nm ultra thin SOI MOSFETs with thin buried oxide. Fifth workshop of the thematic network on silicon on insulator technology, devices and circuits, EUROSOI’09, Göteborg, Sweden, pp. 27–28 (2009)Google Scholar
  20. 20.
    Rudenko, T., Kilchytska, V., Burignat, S., Raskin, J.-P., Andrieu, F., Faynot, O., Nazarov, A., Flandre, D.: Transconductance and mobility behaviors in UTB SOI MOSFETs with standard and thin BOX. Fifth workshop of the thematic network on silicon on insulator technology, devices and circuits, EUROSOI’09, Göteborg, Sweden, pp. 111–112 (2009) Google Scholar
  21. 21.
    Kah-Wee, Ang., Jianqiang, Lin., Chih-Hang, Tung., Balasubramanian, N., Samudra, G.S., Yee-Chia, Yeo.: Strained n-MOSFET with embedded source/drain stressors and strain-transfer structure (STS) for enhanced transistor performance. IEEE Trans. Electron Devices 55, 850–857 (2008)CrossRefGoogle Scholar
  22. 22.
    Néau, G., Martinez, F., Valenza, M., Vildeuil, J.C., Vincent, E., Boeuf, F., Payet, F., Rochereau, K.: Impact of strained-channel n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements. Microelectron. Reliab. 47, 567–572 (2007)CrossRefGoogle Scholar
  23. 23.
    Olsen, S.H., Escobedo-Cousin, E., Varzgar, J.B., Agaiby, R., Seger, J., Dobrosz, P., Chattopadhyay, S., Bull, S.J., O’Neill, A.G., Hellstrom, P.-E., Edholm, J., Ostling, M., Lyutovich, K.L., Oehme, M., Kasper, E.: Control of self-heating in thin virtual substrate strained Si MOSFETs. IEEE Trans. Electron Devices 53, 2296–2305 (2006)CrossRefGoogle Scholar
  24. 24.
    Larson, J.M., Snyder, J.: Overview and status of metal S/D Schottkybarrier MOSFET technology. IEEE Trans. Electron Devices 53, 1048–1058 (2006)CrossRefGoogle Scholar
  25. 25.
    Pearman, D.J., Pailloncy, G., Raskin, J.P., Larson, J.M., Whall, T.E.: Static and high-frequency behavior and performance of Schottky Barrier p-MOSFET devices. IEEE Trans. Electron Devices 54, 2796–2802 (2007)CrossRefGoogle Scholar
  26. 26.
    Raskin, J.P., Pearman, D.J., Pailloncy, G., Larson, J.M., Snyder, J., Leadley, D.L., Whall, T.E.: High-frequency performance of Schottky Barrier p-MOSFET devices. IEEE Electron Device Lett. 29, 396–398 (2008)CrossRefGoogle Scholar
  27. 27.
    Larrieu, G., Dubois, E., Valentin, R., Breil, N., Danneville, F., Dambrine, G., Raskin, J.-P., Pesant, J.-C.: Low temperature implementation of dopant-segregated band-edge metallic S/D junctions in thin-body SOI p-MOSFETs. IEEE Int. Electron Devices Meet., Washington, DC, USA, pp. 147–150 (2007)Google Scholar
  28. 28.
    Valentin, R., Dubois, E., Raskin, J.-P., Larrieu, G., Dambrine, G., Lim Tao, C., Breil, N., Danneville, F.: RF small signal analysis of Schottky-Barrier p-MOSFET. IEEE Trans. Electron Devices 55, 1192–1202 (2008)CrossRefGoogle Scholar
  29. 29.
    Ricco, B., Versari, R., Esseni, D.: Characterization of polysilicon-gate depletion in MOS structures. IEEE Electron Device Lett. 17, 103–105 (1996)CrossRefGoogle Scholar
  30. 30.
    Vandooren, A., Thean, A.V.Y., Du, Y., To, I., Hughes, J., Stephens, T., Huang, M., Egley, S., Zavala, M., Sphabmixay, K., Barr, A., White, T., Samavedam, S., Mathew, L., Schaeffer, J., Triyoso, D., Rossow, M., Roan, D., Pham, D., Rai, R., Nguyen, B.-Y., White, B., Orlowski, M., Duvallet, A., Dao, T., Mogab, J.: Mixed-signal performance of sub-100 nm fully-depleted SOI devices with metal gate, high K (HfO2) dielectric and elevated source/drain extensions. IEEE Int. Electron Devices Meet., Washington, DC, USA, pp. 11.5.1–11.5.3 (2003)Google Scholar
  31. 31.
    Ko, C.H., Kuan, T.M., Zhang, K., Tsai, G., Seutter, S.M., Wu, C.H., Wang, T.J., Ye, C.N., Chen, H.W., Ge, C.H., Wu, K.H., Lee, W.C.: A novel CVD-SiBCN low-K spacer technology for high-speed applications. Symposium on VLSI Technology, Honolulu, Hawaii, USA, pp. 108–109 (2008)Google Scholar
  32. 32.
    Bao, T.I., Chen, H.C., Lee, C.J., Lu, H.H., Shue, S.L., Yu, C.H.: Low capacitance approaches for 22 nm generation Cu interconnect. International symposium on VLSI technology, systems, and applications, Hsinchu, Taiwan, pp. 51–56 (2009)Google Scholar
  33. 33.
    Ernst, T., Tinella, C., Raynaud, C., Cristoloveanu, S.: Fringing fields in sub-0.1 μm fully depleted SOI MOSFET’s: optimization of the device architecture. Solid State Electron. 46, 373–378 (2002)CrossRefGoogle Scholar
  34. 34.
    Fujiwara, M., Fujiwara, M., Morooka, T., Yasutake, N., Ohuchi, K., Aoki, N., et al.: Impact of BOX scaling on 30 nm gate length FD SOI MOSFET. IEEE international SOI conference, Honolulu, Hawaii, USA, pp. 180–182 (2005)Google Scholar
  35. 35.
    Gianesello, F., Gloria, D., Raynaud, C., Montusclat, S., Boret, S., Clement, C., Benech, P.H., Fournier, J.M., Dambrine, G.: State of the art 200 GHz passive components and circuits integrated in advanced thin SOI CMOS technology on high resistivity substrate. IEEE international SOI conference, Niagara Falls, New York, USA, pp. 121–122 (2006)Google Scholar
  36. 36.
    Gianesello, F., Gloria, D., Raynaud, C., Montusclat, S., Boret, S., Touret, P.: On the design of high performance RF integrated inductors on high resistively thin film 65 nm SOI CMOS technology. IEEE topical meeting on silicon monolithic integrated circuits in RF systems, pp. 98–101 (2008)Google Scholar
  37. 37.
    Kinoshita, T., Hasumi, R., Hamaguchi, M., Miyashita, K., Komoda, T., Kinoshita, A., Koga, J., Adachi, K., Toyoshima, Y., Nakayama, T., Yamada, S., Matsuoka, F.: Ultra low voltage operations in bulk CMOS logic circuits with dopant segregated Schottky source/drain transistors. IEEE Int. Electron Devices Meet., pp. 1–4 (2006)Google Scholar
  38. 38.
    Connelly, D., Faulkner, C., Grupp, D.E.: Optimizing Schottky S/D Offset for 25-nm dual-gate CMOS performance. IEEE Electron Device Lett. 24, 411–413 (2003)CrossRefGoogle Scholar
  39. 39.
    Xiong, S., King, T.-J., Bokor, J.: A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drain. IEEE Trans. Electron Devices 52, 1859–1867 (2005)CrossRefGoogle Scholar
  40. 40.
    Jang, M., Kim, Y., Shin, J., Lee, S., Park, K.: A 50-nm-gate-length erbium-silicided n-type Schottky barrier metal-oxide-semiconductor field-effect transistor. Appl. Phys. Lett. 84, 741–743 (2004)CrossRefGoogle Scholar
  41. 41.
    Zhu, S., Chen, J., Li, M.-F., Lee, S.J., Singh, J., Zhu, C.X., Du, A., Tung, C.H., Chin, A., Kwong, D.L.: N-type Schottky barrier source/drain MOSFET using Ytterbium silicide. IEEE Electron Device Lett. 25, 565–567 (2004)CrossRefGoogle Scholar
  42. 42.
    Kedzierski, J., Xuan, P., Anderson, E.H., Bokor, J., King, T.-J., Hu, C.: Complementary silicide source/drain thin-body MOSFETs for the 20 nm gate length regime. IEEE Int. Electron Devices Meet., pp. 57–60 (2000)Google Scholar
  43. 43.
    Luo, J., Qiu, Z.-J., Zhang, D.W., Hellström, P.-E., Östling, M., Zhang, S.-L.: Effects of carbon on Schottky Barrier heights of NiSi modified by dopant segregation. IEEE Electron Device Lett. 30, 608–610 (2009)CrossRefGoogle Scholar
  44. 44.
    Urban, C., Zhao, Q.T., Sandow, C., Müller, M., Breuer, U., Mantl, S.: Schottky barrier height modulation by arsenic dopant segregation. Proceedings of 9th international conference ULIS, pp. 151–154 (2008)Google Scholar
  45. 45.
    Fritze, M., Chen, C.L., Calawa, S., Yost, D., Wheeler, B., Wyatt, P., Keast, C.L., Snyder, J., Larson, J.: High-speed Schottky-barrier pMOSFET with fT = 280 GHz. IEEE Electron Device Lett. 25, 220–222 (2004)CrossRefGoogle Scholar
  46. 46.
    Valentin, R., Dubois, E., Larrieu, G., Raskin, J.-P., Dambrine, G., Breil, N., Danneville, F.: Optimization of RF performance of metallic source/drain SOI MOSFETs using dopant segregation at the Schottky interface. IEEE Electron Device Lett. 30, 1197–1199 (2009)CrossRefGoogle Scholar
  47. 47.
    Urban, C., Emam, M., Sandow, C., Zhao, Q.T., Fox, A., Raskin, J.-P., Mantl, S.: High-frequency performance of dopant-segregated NiSi S/D SOI SB-MOSFETs. Proceedings of 38th ESSDERC, pp. 149–152 (2009)Google Scholar
  48. 48.
    Urban, C., Emam, M., Sandow, C., Knoch, J., Zhao, Q.T., Raskin, J.-P., Mantl, S.: Radio frequency study of dopant-segregated n-type SB-MOSFETs on thin-body SOI. IEEE Electron Device Lett. 31, 537–539 (2010)CrossRefGoogle Scholar
  49. 49.
    Knoch, J., Zhang, M., Zhao, Q.T., St. Lenk, J., Mantl, S., Appenzeller, J.: Effective Schottky barrier lowering in silicon-oninsulator Schottky-barrier metal–oxide–semiconductor field-effect transistors using dopant segregation. Appl. Phys. Lett. doi: 10.1063/1.2150581 (2005)
  50. 50.
    Zhang, M., Knoch, J., Zhao, Q.T., Breuer, U., Mantl, S.: Impact of dopant segregation on fully depleted Schottky-barrier SOI-MOSFETs. Solid State Electron 50(4), 594–600 (2006)CrossRefGoogle Scholar
  51. 51.
    Bracale, A., Ferlet-Cavrois, V., Fel, N., Pasquet, D., Gautier, J.L., Pelloie, J.L., Du Port De Pon-charra, J.: A new approach for SOI devices small-signal parameters extraction. Analog Integr. Circuits Signal Process 25(2), 157–169 (2000)CrossRefGoogle Scholar
  52. 52.
    Raskin, J.-P., Gillon, R., Chen, J., Vanhoenacker-Janvier, D., Colinge, J.-P.: Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modelling. IEEE Trans. Electron Devices 45(5), 1017–1025 (1998)CrossRefGoogle Scholar
  53. 53.
    Colinge, J.-P., Gao, M.-H., Romano, A., Maes, H., Claeys, C.: Silicon-on-insulator ‘gate-all-around’ MOS device. Proceedings of IEEE SOS/SOI technical conference, Key West, Florida, USA, pp. 137–138 (1990)Google Scholar
  54. 54.
    Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., Hu, C.: FinFET—a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)CrossRefGoogle Scholar
  55. 55.
    Cristoloveanu, S.: Silicon on insulator technologies and devices: from present to future. Solid State Electron 45(8), 1403–1411 (2001)CrossRefGoogle Scholar
  56. 56.
    Park, J.-T., Colinge, J.-P.: Multiple-gate SOI MOSFETs: device design guidelines. IEEE Trans. Electron Devices 49(12), 2222–2229 (2002)CrossRefGoogle Scholar
  57. 57.
    Kedzierski, J., Fried, D.M., Nowak, E.J., et al.: High performance symmetric-gate and CMOS-compatible Vt asymmetric-gate FinFET devices. IEEE International Electron Devices Meeting—IEDM, Washington, DC, USA, pp. 437–440 (2001)Google Scholar
  58. 58.
    Woo, D.-S., Lee, J.-H., Choi, W.Y., Choi, B.Y., Choi, Y.J., Lee, J.D., Park, B.-G.: Electrical characteristics of FinFET with vertically nonuniform source/drain profile. IEEE Trans. Nanotech. 1(4), 233–237 (2002)CrossRefGoogle Scholar
  59. 59.
    Kilchytska, V., Collaert, N., Rooyackers, R., Lederer, D., Raskin, J.-P., Flandre, D.: Perspective of FinFETs for analog applications. 34th European solid-state device research conference—ESSDERC 2004, Leuven, Belgium, pp. 65–68 (2004)Google Scholar
  60. 60.
    Lederer, D., Kilchytska, V., Rudenko, T., Collaert, N., Flandre, D., Dixit, A., De Meyer, K., Raskin, J.-P.: FinFET analog characterization from DC to 110 GHz. Solid State Electron. 49, 1488–1496 (2005)CrossRefGoogle Scholar
  61. 61.
    Dixit, A., Kottantharayil, A., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K.: Analysis of the parasitic source/drain resistance in multiple gate field effect transistors. IEEE Trans. Electron Dev. 52(6), 1131–1140 (2005)CrossRefGoogle Scholar
  62. 62.
    Razavi, B., Ran-Hong, Y., Lee Kwing, F.: Impact of distributed gate resistance on the performance of MOS devices. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 41(11), 750–754 (1994)CrossRefGoogle Scholar
  63. 63.
    Wen, W., Mansun, C.: Analysis of geometry-dependent parasitics in Multifin double-gate FinFETs. IEEE Trans. Electron Devices 54(4), 692–698 (2007)CrossRefGoogle Scholar
  64. 64.
    Moldovan, O., Lederer, D., Iniguez, B., Raskin, J.-P.: Finite element simulations of parasitic capacitances related to multiple-gate field-effect transistors architectures. The 8th topical meeting on silicon monolithic integrated circuits in RF systems—SiRF 2008, Orlando, FL, USA, pp. 183–186 (2008)Google Scholar
  65. 65.
    Raskin, J.-P., Chung, T.M., Kilchytska, V., Lederer, D., Flandre, D.: Analog/RF performance of multiple-gate SOI devices: wideband simulations and characterization. IEEE Trans. Electron Devices 53, 1088–1094 (2006)CrossRefGoogle Scholar
  66. 66.
    Raskin, J.-P., Pailloncy, G., Lederer, D., Danneville, F., Dambrine, G., Decoutere, S., Mercha, A., Parvais, B.: High frequency noise performance of 60 nm gate length FinFETs. IEEE Trans. Electron Devices 55, 2718–2727 (2008)CrossRefGoogle Scholar
  67. 67.
    Gianesello, F., Montusclat, S., Martineau, B., Gloria, D., Raynaud, C., Boret, S., Dambrine, G., Lepilliet, S., Pilard, R.: 1.8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS technology. IEEE radio frequency integrated circuits (RFIC) symposium, Hawaï, USA, pp. 555–558 (2007)Google Scholar
  68. 68.
    Lederer, D., Raskin, J.-P.: Effective resistivity of fully-processed high resistivity wafers. Solid State Electron. 49, 491–496 (2005)CrossRefGoogle Scholar
  69. 69.
    Heinrich, W.: Quasi-TEM description of MMIC coplanar lines including conductor-loss effects. IEEE Trans. Microw. Theory Tech. 41, 45–52 (1993)CrossRefGoogle Scholar
  70. 70.
    Reyes, A.C., El-Ghazaly, S.M., Dom, S.J., Dydyk, M., Schroeder, D.K., Patterson, H.: Coplanar waveguides and microwave inductors on silicon substrates. IEEE Trans. Microw. Theory Tech. 43, 2016–2021 (1995)CrossRefGoogle Scholar
  71. 71.
    Benaissa, K., Yuan, J.-T., Crenshaw, D., Williams, B., Sridhar, S., Ai, J., Boselli, G., Zhao, S., Tang, S., Ashbun, S., MAdhani, P., Blythe, T., Mahalingam, N., Schichijo, H.: RF CMOS high-resistivity substrates for systems-on-chip applications. IEEE Trans. Electron Devices 50, 567–576 (2003)CrossRefGoogle Scholar
  72. 72.
    Wu, Y., Gamble, H.S., Armstrong, B.M., Fusco, V.F., Stewart, J.A.C.: SiO2 interface layer effects on microwave loss of high-resistivity CPW line. IEEE Microw. Guid. Wave Lett. 9, 10–12 (1999)CrossRefGoogle Scholar
  73. 73.
    Lederer, D., Desrumeaux, C., Brunier, F., Raskin, J.-P.: High resistivity SOI substrates: how high should we go? In: Proceedings of IEEE international SOI conference, Newport Beach, CA, USA, pp. 50–51 (2003)Google Scholar
  74. 74.
    Schollhorn, C., Zhao, W., Morschbach, M., Kasper, E.: Attenuation mechanisms of aluminum millimeter-wave coplanar waveguides on silicon. IEEE Trans. Electron Devices 50, 740–746 (2003)CrossRefGoogle Scholar
  75. 75.
    Lu, H.-C., Chu, T.-H.: The thru-line-symmetry (TLS) calibration method for on-wafer scattering matrix measurement of four-port networks. IEEE MTT-S international microwave symposium digest, Fort Worth, TX, USA, pp. 1801–1804 (2004)Google Scholar
  76. 76.
    Gamble, H., Armstrong, B.M., Mitchell, S.J.N., Wu, Y., Fusco, V.F., Stewart, J.A.C.: Low-loss CPW lines on surface stabilized high resistivity silicon. IEEE Microw. Guid. Wave Lett. 9, 395–397 (1999)CrossRefGoogle Scholar
  77. 77.
    Wong, B., Burghartz, J.N., Natives, L.K., Rejaei, B., van der Zwan, M.: Surface-passivated high resistivity silicon substrates for RFICs. IEEE Electron Device Lett. 25, 176–178 (2004)CrossRefGoogle Scholar
  78. 78.
    Lederer, D., Raskin, J.-P.: New substrate passivation method dedicated to high resistivity SOI wafer fabrication with increase substrate resistivity. IEEE Electron Device Lett. 26, 805–807 (2005)CrossRefGoogle Scholar
  79. 79.
    Calmon, F., Andrei, C., Valorge, O., Perez, J.-C., Verdier, J., Nunez, J., Gontrand, C.H.: Impact of low-frequency substrate disturbances on a 4.5 GHz VCO. Microelectron. J. 37, 1119–1127 (2006)CrossRefGoogle Scholar
  80. 80.
    Van Heijningen, M., Badaroglu, M., Donnay, S., Engels, M., Bolsen, I.: High-level simulation of substrate noise generation including power supply noise coupling. 37th conference on design automation—DAC 2000, Los Angeles, CA, USA, pp. 46–451 (2000)Google Scholar
  81. 81.
    Lederer, D., Raskin, J.-P.: Bias effects on RF passive structures in HR Si substrates. In: Proceedings of 6th topical meeting silicon microwave. integrative circuits RF systems, pp. 8–11 (2006)Google Scholar
  82. 82.
    Van Heijningen, M., Compiet, J., Wambacq, P., Donnay, S., Engels, M.G.E., Bolsens, I.: Analysis and experimental verification of digital substrate noise generation for epi-type substrates. IEEE J. Solid State Circuits 35, 1002–1008 (2000)CrossRefGoogle Scholar
  83. 83.
    Van Heijningen, M., Badaroglu, M., Donnay, S., Gielen, G.G.E., De Man, H.J.: Substrate noise generation in complex digital systems: efficient modeling and simulation methodology and experimental verification. IEEE J. Solid State Circuits 37, 1065–1072 (2002)CrossRefGoogle Scholar
  84. 84.
    Badaroglu, M., Donnay, S., De Man, H.J., Zinzius, Y.A., Gielen, G.G.E., Sansen, W., Fonden, T., Signell, S.: Modeling and experimental verification of substrate noise generation in a 220-kgates wlan system-on-chip with multiple supplies. IEEE J. Solid State Circuits 38, 1250–1260 (2003)CrossRefGoogle Scholar
  85. 85.
    Jenkins, K.A., Rhee, W., Liobe, J., Ainspan, H.: Experimental analysis of the effect of substrate noise on PLL. In: Proceedings of 6th topical meeting silicon monolithic integrative circuits RF systems, San Diego, CA, pp. 54–57 (2006)Google Scholar
  86. 86.
    ITRS Roadmap: Front end processes. http://www.itrs.net/Common/2005ITRS/FEP2005.pdf (2005)
  87. 87.
    Neve, C., Roda, B.D., Ambroise, R., Flandre, D., Raskin, J.-P.: Comparison of digital substrate noise in SOI and Bulk Si CMOS technologies. 7th workshop on low-voltage low power design, Louvain-la-Neuve, Belgium, pp. 23–28 (2008)Google Scholar
  88. 88.
    Bol, D., Ambroise, R., Neve, C., Roda, C., Raskin, J.-P., Flandre, D.: Wide-band simulation and characterization of digital substrate noise in SOI technology. IEEE international SOI conference, Indian Wells, CA, USA, pp. 133–134 (2007)Google Scholar
  89. 89.
    Chen, H.H., Ling, D.D.: Power supply noise analysis methodology For deep-submicron VLSI chip design proceedings of the 34th design automation, Anaheim, CA, USA, pp. 638–643 (1997)Google Scholar
  90. 90.
    Tinella, C., Richard, O., Cathelin, A., Reaute, F., Majcherczak, S., Blanchet, F., Belot, D.: 0.13 μm CMOS SOI SP6T antenna switch for multi-standard handsets. Topical meeting on silicon monolithic integrated circuits in RF systems, pp. 58 (2006)Google Scholar
  91. 91.
    McKay, T.G., Carroll, M.S., Costa, J., Iversen, C., Kerr, D.C., Remoundos, Y.: Linear cellular antenna switch for highly integrated SOI front-end. IEEE Intl. SOI Conf. (2007)Google Scholar
  92. 92.
    Single-pole four-throw high-power switch RF1450 Data sheet. http://www.rfmd.com/pdfs/1450DS.pdf

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  1. 1.Institute of Information and Communication Technologies, Electronics and Applied Mathematics (ICTEAM)Université catholique de Louvain (UCL)Louvain-la-NeuveBelgium

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