Confined and Guided Vapor–Liquid–Solid Catalytic Growth of Silicon Nanoribbons: From Nanowires to Structured Silicon-on-Insulator Layers

  • A. Lecestre
  • E. DuboisEmail author
  • A. Villaret
  • T. Skotnicki
  • P. Coronel
  • G. Patriarche
  • C. Maurice
Part of the Engineering Materials book series (ENG.MAT.)


The stacking of crystal semiconductor thin films alternated with dielectric layers continuously arouses a sustained interest for its utility in three-dimensional (3D) integration of metal-oxide-semiconductor field-effect transistor (MOSFET). However, the growth of crystalline silicon without resorting to epitaxial growth from a crystal seed still constitutes an unresolved challenge. Although many different techniques ranging from solid-phase crystallization to thin-film bonding constitutes possible solutions with their respective advantages and weaknesses, little attention has been paid so far to the adaptation of a technique widely used for producing semiconductor nanowires, namely, the vapor–liquid–solid (VLS) catalytic growth. The basic idea developed in this chapter is to control VLS growth for synthesizing local silicon-on-insulator (SOI) layers at reduced thermal budget. Confined VLS growth is therefore proposed to produce single crystalline silicon (c-Si) film over an amorphous oxide layer, without crystalline seeding. It is demonstrated that VLS growth in the spatial confinement of a cavity produces nanometer-thick c-Si ribbons over a micron area scale with a well controlled localization. The nature of grown silicon layers is characterized by SEM (Scanning Electron Microscopy), EBSD (Electron Backscattered Diffraction) and STEM (Scanning Transmission Electron Microscopy) to analyze its crystallinity and to check the impact of the confining cavity walls on the purity of grown silicon. Beyond the in-depth structural analysis of VLS grown nanoribbons, simple back-gated MOSFET structures have been fabricated and electrically characterized to extract transport properties. The obtained hole mobility of 53 cms−1 V−1 constitutes an excellent compromise for a processing temperature less or equal to 500°C.


Twin Boundary Electron Backscatter Diffraction Amorphous Substrate Transmission Electron Microscopy Characterization Wide Cavity 
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  1. 1.
    Sakuma, K., Andry, P.S., Tsang, C.K., Wright, S.L., Dang, B., Patel, C.S., Webb, B.C., Maria, J., Sprogis, E.J., Kang, S.K., Polastre, R.J., Horton, R.R., Knickerbocker, J.U.: 3D Chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. IBM J. Res. Dev. 52, 611–622 (2008)CrossRefGoogle Scholar
  2. 2.
    Lim, H., Jung, S.M., Rah, Y., Ha, T., Park, H., Chang, C., Cho, W., Park, J., Son, B., Jeong, J., Cho, H., Choi, B., Kim, K.: 65 nm high performance SRAM technology with 25F2 0.16 μm2 S3 (stacked single-crystal Si) SRAM cell. Solid-State Device Research Conference, ESSDERC, Proc IEEE, pp. 549–552 (2005)Google Scholar
  3. 3.
    Mimura, A., Konishi, N., Ono, K., Ohwada, J.-I., Hosokawa, Y., Ono, Y.A., Suzuki, T., Miyata, K., Kawakami, H.: High-performance low temperature poly-Si n-channel TFT’s for LCD’s. IEEE Trans. Electron. Devices 36, 351–359 (1989)CrossRefGoogle Scholar
  4. 4.
    Subramanian, V., Dankoski, P., Degertekin, L., Khuri-Yakub, B.T., Saraswat, K.C.: Controlled two-step solid-phase crystallization for high performance polysilicon TFT’s. IEEE Trans. Electron. Devices 18, 378–381 (1997)CrossRefGoogle Scholar
  5. 5.
    Hatalis, M.K., Greve, D.W.: High-performance thin-film transistors in low-temperature crystallized LPCVD amorphous silicon films. IEEE Electron. Device Lett. 8, 361–364 (1987)CrossRefGoogle Scholar
  6. 6.
    Sheu, J.T., Huang, P.C., Sheu, T.S., Chen, C.C., Chen, L.A.: Characteristics of GAA twin poly-Si NW TFT. IEEE Electron. Device Lett. 30, 139–141 (2009)CrossRefGoogle Scholar
  7. 7.
    Hekmatshoar, B., Cherenack, K.H., Kattamis, A.Z., Long, K., Wagner, S., Stur, J.C.: Highly stable amorphous-silicon thin-film transistors on clear plastic. APL 93, 032103 (2008)Google Scholar
  8. 8.
    Yamauchi, N., Hajjar, J.J., Reif, R.: Drastically improved performance in poly-Si TFT with channel dimensions comparable to grain size. Technical Digest of International Electron Devices Meeting 1989, IEDM’89, pp. 353–356 (1989)Google Scholar
  9. 9.
    Pan, T.M., Chan, C.L., Wu, T.W.: High-performance poly-silicon TFTs using a high-k PrTiO3 gate dielectric. IEEE Electron. Device Lett. 30, 39–41 (2009)CrossRefGoogle Scholar
  10. 10.
    Oh, J.H., Kang, D.H., Park, W.H., Jang, J., Chang, Y.J., Choi, J.B., Kim, C.W.: A center-offset polycrystalline-Si TFT with n+ amorphous Si contacts. IEEE Electron. Device Lett. 30, 36–38 (2009)CrossRefGoogle Scholar
  11. 11.
    Zhang, D., Kwok, H.S.: A reduced mask-count technology for complementary polycrystalline silicon TFT with self-aligned metal electrodes. IEEE Electron. Device Lett. 30, 33–35 (2009)CrossRefGoogle Scholar
  12. 12.
    Chang, C.P., Wu, Y.C.S.: Improved electrical performance and uniformity of MILC poly-Si TFTs manufactured using drive-in nickel-induced lateral crystallization. IEEE Electron. Device Lett. 30, 1176–1178 (2009)CrossRefGoogle Scholar
  13. 13.
    Lee, S.-W., Joo, S.-K.: Low temperature poly-Si thin film transistor fabrication by metal induced lateral crystallization. IEEE Electron. Device Lett. 17, 160–162 (1996)CrossRefGoogle Scholar
  14. 14.
    Meng, Z., Wang, M., Wong, M.: High performance low temperature metal-induced unilaterally crystallized polycrystalline silicon thin film transistors for system-on-panel applications. IEEE Trans. Electron. Devices 47, 404–409 (2000)CrossRefGoogle Scholar
  15. 15.
    Kim, J.C., Choi, J.H., Kim, S.S., Jang, J.: Stable polycrystalline silicon TFT with MICC. IEEE Electron. Device Lett. 25, 182–184 (2004)CrossRefGoogle Scholar
  16. 16.
    Hu, C.M., Wu, Y.S., Lin, C.C.: Improving the electrical properties of NILC poly-Si films using a gettering substrate. IEEE Electron. Device Lett. 28, 1000–1003 (2007)CrossRefGoogle Scholar
  17. 17.
    Chang, C.P., Wu, Y.S.: Improved electrical characteristics and reliability of MILC poly-Si TFTs using fluorine-ion implantation. IEEE Electron. Device Lett. 28, 990–992 (2007)CrossRefGoogle Scholar
  18. 18.
    Song, N.K., Kim, Y.S., Kim, M.S., Han, S.H., Joo, S.K.: A fabrication method for reduction of silicide contamination in polycrystalline silicon thin-film transistors. Electrochem. Solid-State Lett. 10, H142–H144 (2007)CrossRefGoogle Scholar
  19. 19.
    Sameshima, T., Usui, S., Sekiya, M.: XeCl excimer laser annealing used in the fabrication of poly-Si TFT’s. IEEE Electron. Device Lett. 7, 276–278 (1986)CrossRefGoogle Scholar
  20. 20.
    Brunets, I., Holleman, J., Kovalgin, A.Y., Boogaard, A., Schmitz, J.: Low-temperature fabricated TFTs on polysilicon stripes. IEEE Trans. Electron. Devices 56, 1637–1644 (2009)CrossRefGoogle Scholar
  21. 21.
    Hara, A., Takeuchi, F., Takei, M., Suga, K., Yoshino, K., Chida, M., Sano, Y., Sasaki, N.: High-performance polycrystalline silicon thin film transistors on non alkali glass produced using continuous wave laser crystallization. Jpn. J. Appl. Phys. 41, L311–L313 (2002)CrossRefGoogle Scholar
  22. 22.
    Ishihara, R., Matsumura, M.: Excimer-laser-produced single-crystal silicon thin film transistors. Jpn. J. Appl. Phys. 36, 6167–6170 (1997)CrossRefGoogle Scholar
  23. 23.
    Hara, A., Takeuchi, F., Sasaki, N.: Mobility enhancement limit of excimer-laser-crystallized. J. Appl. Phys. 91, 708–714 (2002)CrossRefGoogle Scholar
  24. 24.
    Uchikoga, S., Ibaraki, N.: Low temperature poly Si TFT-LCD by excimer laser anneal. Thin Solid Films 383, 19–24 (2001)CrossRefGoogle Scholar
  25. 25.
    Im, J.S., Kim, H.J., Thompson, M.O.: Phase transformation mechanisms involved in excimer laser crystallization of amorphous silicon films. Appl. Phys. Lett. 63, 1969–1971 (1993)CrossRefGoogle Scholar
  26. 26.
    Im, J.S., Kim, H.J.: On the super lateral growth phenomenon observed in excimer laser-induced crystallization of thin Si films. Appl. Phys. Lett. 64, 2303–2305 (1994)CrossRefGoogle Scholar
  27. 27.
    Crowder, M.A., Carey, P.G., Smith, P.M., Sposili, R.S., Cho, H.S., Im, J.S.: Low-temperature single-crystal Si TFT’s fabricated on Si films processed via sequential lateral solidification. IEEE Electron. Device Lett. 19, 3006–3008 (1998)CrossRefGoogle Scholar
  28. 28.
    Crowder, M.A., Voutsas, A.T., Droes, S.R., Moriguchi, M., Mitani, Y.: Sequential lateral solidification processing for polycrystalline Si TFTs. IEEE Electron. Device Lett. 51, 558–560 (2004)Google Scholar
  29. 29.
    Yin, H., Xianyu, W., Cho, H., Zhang, X., Jung, J., Kim, D., Lim, H., Park, K., Kim, J., Kwon, J., Noguchi, T.: Advanced poly-Si TFT with fin-like channels by ELA. IEEE Electron. Device Lett. 27, 357–359 (2006)CrossRefGoogle Scholar
  30. 30.
    Yin, H., Xianyu, W., Tikhonovsky, A., Park, Y.S.: Scalable 3-D finlike poly-Si TFT and its nonvolatile memory application. IEEE Trans. Electron. Devices 55, 578–584 (2008)CrossRefGoogle Scholar
  31. 31.
    Van der Wilt, P.C., van Dijk, B.D., Bertens, G.J., Ishihara, R., Beenakker, C.I.M.: Formation of location-controlled crystalline islands using substrate-embedded-seeds in excimer-laser crystallization of silicon film. Appl. Phys. Lett. 79, 1819–1822 (2001)CrossRefGoogle Scholar
  32. 32.
    Baiano, A., Danesh, M., Saputra, N., Ishihara, R., Long, J., Metselaar, W., Beenakker, C.I.M., Karaki, N., Hiroshima, Y., Inoue, S.: Single-grain Si thin-film transistors SPICE model, analog and RF circuit applications. Solid-State Electron. 52, 1345–1352 (2008)CrossRefGoogle Scholar
  33. 33.
    Rana, V., Ishihara, R., Hiroshima, Y., Abe, D., Inoue, S., Shimoda, T., Metselaar, W., Beenakker, K.: Dependence of single-crystalline Si TFT characteristics on the channel position inside a localisation-controlled grain. IEEE Trans. Electron. Devices 52, 2622–2628 (2005)CrossRefGoogle Scholar
  34. 34.
    Ishihara, R., van der Wilt, P.C., van Dijk, B.D., Burtsev, A., Voogt, F.C., Bertens, G.J., Metselaar, J.W., Beenakker, C.I.M., Edward, T.V., Kelley, F.: Advanced excimer laser crystallization techniques of Si thin-film for location-control of large grain on glass. Flat Panel Disp. Technol. Disp. Metrol. II 4295, 14–23 (2001)Google Scholar
  35. 35.
    Baiano, A., Ishihara, R., van der Cingel, J., Beenakker, K.: Strained single-grain silicon n- and p-channel TFT by excimer laser. IEEE Electron. Device Lett. 31, 308–310 (2010)CrossRefGoogle Scholar
  36. 36.
    Sato, T., Yamamoto, K., Kambara, J., Kitahara, K., Hara, A.: Fabrication of large lateral polycrystalline silicon film by laser dehydrogenation and lateral crystallization of hydrogenated nanocrystalline silicon films. Jpn. J. Appl. Phys. 48, 121201–121206 (2009)CrossRefGoogle Scholar
  37. 37.
    Han, S.M., Lee, M.C., Shin, M.Y., Park, J.H., Han, M.K.: Poly-Si TFT fabricated at 150°C using ICP-CVD and excimer laser annealing. Proc. IEEE 93, 1297–1305 (2005)CrossRefGoogle Scholar
  38. 38.
    Ishihara, R., He, T.M., Rana, V., Hiroshima, Y., Inoue, S., Shimoda, T., Metselaar, J.W., Beenakker, C.I.M.: Electrical property of coincidence site lattice grain boundary in location-controlled Si island by excimer-laser crystallisation. Thin Solid Films 487, 97–101 (2005)CrossRefGoogle Scholar
  39. 39.
    Wagner, R.S., Ellis, W.C.: Vapor–liquid–solid mechanism of crystal growth and its application to silicon. Appl. Phys. Lett. 4, 89–90 (1964)CrossRefGoogle Scholar
  40. 40.
    Ke, Y., Weng, X., Redwing, J.M., Eichfeld, C.M., Swisher, T.R., Mohney, S.E., Habib, Y.M.: Fabrication and electrical properties of Si nanowires synthesized by Al catalyzed VLS growth. Nano Lett. 9, 4494–4499 (2009)CrossRefGoogle Scholar
  41. 41.
    Lu, W., Lieber, C.M.: Topical review: semiconductor nanowires. J. Phys. D Appl. Phys. 39, R387 (2006)CrossRefGoogle Scholar
  42. 42.
    Schmidt, V., Wittemann, J.V., Senz, S., Gösele, U.: Silicon nanowires: a review on aspects of their growth and their electrical properties. Adv. Mater. 21, 2681–2702 (2009)CrossRefGoogle Scholar
  43. 43.
    Quitoriano, N.J., Kamins, T.I.: Integrable nanowire transistors. Nano Lett. 8, 4410–4414 (2008)CrossRefGoogle Scholar
  44. 44.
    Fan, H.J., Werner, P., Zacharias, M.: Semiconductor nanowires: from self-organization to patterned growth. Small 2, 700–717 (2006)CrossRefGoogle Scholar
  45. 45.
    Schmidt, V., Senz, S., Gösele, U.: Diameter-dependent growth direction of epitaxial silicon nanowires. Nano Lett. 5, 931–935 (2005)CrossRefGoogle Scholar
  46. 46.
    Persson, A.I., Larsson, M.L., Stenström, S., Ohlsson, B.J., Samuelson, L., Wallenberg, L.R.: Solid-phase diffusion mechanism for GaAs nanowire growth. Nat. Mater. 3, 677–681 (2004)CrossRefGoogle Scholar
  47. 47.
    Lugstein, A., Steinmair, M., Hyun, Y.J., Hauer, G., Pongratz, P., Bertagnolli, E.: Pressure-induced orientation control of the growth of epitaxial silicon nanowires. Nano Lett. 8, 2310–2314 (2008)CrossRefGoogle Scholar
  48. 48.
    Shimizu, T., Zhang, Z., Shingubara, S., Senz, S., Gösele, U.: Vertical epitaxial wire-on-wire growth of Ge/Si on Si(100) substrate. Nano Lett. 9, 1523–1526 (2009)CrossRefGoogle Scholar
  49. 49.
    Lew, K.K., Redwing, J.M.: Growth characteristics of silicon nanowires synthesized by vapor–liquid–solid growth in nanoporous alumina templates. J. Cryst. Growth 254, 14–22 (2003)Google Scholar
  50. 50.
    Shan, Y., Ashok, S., Fonash, S.J.: Unipolar accumulation-type transistor configuration implemented using Si nanowires. Appl. Phys. Lett. 91, 093518–093520 (2007)CrossRefGoogle Scholar
  51. 51.
    Shan, Y., Kalkan, A.K., Peng, C.Y., Fonash, S.J.: From Si source gas directly to positioned, electrically contacted Si nanowires: the self-assembling “Grow-in-place” approach. Nano Lett. 4, 2085–2089 (2004)CrossRefGoogle Scholar
  52. 52.
    Shan, Y., Fonash, S.J.: Self-assembling silicon nanowires for device applications using the nanochannel-guided “Grow-in-place” approach. ACS Nano 2, 429–434 (2008)CrossRefGoogle Scholar
  53. 53.
    Lecestre, A., Dubois, E., Villaret, A., Coronel, P., Skotnicki, T., Delille, D., Maurice, C., Troadec, D.: Confined and guided catalytic growth of crystalline silicon films on a dielectric substrate. IOP Conf. Ser. Mater. Sci. Eng. 6, 012022 (2009)CrossRefGoogle Scholar
  54. 54.
    Hannon, J.B., Kodambaka, S., Ross, F.M., Tromp, R.M.: The influence of the surface migration of gold on the growth of silicon nanowires. Nature 440, 69–71 (2006)CrossRefGoogle Scholar
  55. 55.
    Allen, J.E., Hemesath, E.R., Perea, D.E., Lensch-Falk, J.L., Li, Z.Y., Yin, F., Gass, M.H., Wang, P., Bleloch, A.L., Palmer, R.E., Lauhon, L.J.: High-resolution detection of Au catalyst atoms in Si nanowires. Nat. Nanotechnol. 3, 168–173 (2008)CrossRefGoogle Scholar
  56. 56.
    den Hertog, M.I., Rouviere, J.L., Dhalluin, F., Desre, P.J., Gentile, P.P., Ferret, P., Oehler, F., Baron, T.: Control of gold surface diffusion on Si nanowires. Nano Lett. 8, 1544–1550 (2008)CrossRefGoogle Scholar
  57. 57.
    Lecestre, A., Dubois, E., Villaret, A., Skotnicki, T., Coronel, P., Patriarche, G., Maurice, C.: Confined VLS growth and structural characterization of silicon nanoribbons. Microelectron. Eng. 87, 1522–1526 (2010)CrossRefGoogle Scholar
  58. 58.
    Cristoloveanu, S., Munteanu, D., Liu, M.S.T.: A review of the pseudo-MOS transistor in SOI wafers: operation, parameter extraction, and applications. IEEE Trans. Electron. Devices 47, 1018–1027 (2000)CrossRefGoogle Scholar
  59. 59.
    Sato, S., Komiya, K., Bresson, N., Omura, Y., Cristoloveanu, S.: Possible influence of the Schottky contacts on the characteristics of ultrathin SOI pseudo-MOS transistors. IEEE Trans. Electron. Devices 52, 1807–1814 (2005)CrossRefGoogle Scholar
  60. 60.
    Larrieu, G., Dubois, E., Wallart, X., Baie, X., Katcki, J.: Formation of Pt-based silicide contacts: kinetics, stoichiometry and current drive capabilities. J. Appl. Phys. 94, 7801–7810 (2003)CrossRefGoogle Scholar
  61. 61.
    Dubois, E., Larrieu, G.: Measurement of low Schottky barrier heights applied to metallic source/drain MOSFETs. J. Appl. Phys. 96, 729–737 (2004)CrossRefGoogle Scholar
  62. 62.
    Breil, N., Dubois, E., Halimaoui, A., Pouydebasque, A., Larrieu, G., Łaszcz, A., Ratajcak, J., Skotnicki, T.: Integration of PtSi in p-type MOSFETs using a sacrificial low-temperature germanidation process. IEEE Electron. Device Lett. 29, 152–154 (2008)CrossRefGoogle Scholar
  63. 63.
    Breil, N., Halimaoui, A., Dubois, E., Larrieu, G., Łaszczc, A., Ratajczakc, J., Rolland, G., Pouydebasquee, A., Skotnicki, T.: Selective etching of Pt with respect to PtSi using a sacrificial low temperature germanidation process. Appl. Phys. Lett. 91, 232112 (2007)CrossRefGoogle Scholar
  64. 64.
    Reckinger, N., Tang, X., Bayot, V., Yarekha, D., Dubois, E., Godey, S., Wallart, X., Larrieu, G., Laszcz, A., Ratajczak, J., Jacques, P., Raskin, J.P.: Schottky barrier lowering with the formation of crystalline Er silicide on n-Si upon thermal annealing. Appl. Phys. Lett. 94, 191913 (2009)CrossRefGoogle Scholar
  65. 65.
    Yarekha, D., Larrieu, G., Breil, N., Dubois, E., Godey, S., Wallart, X., Soyer, C., Remiens, D., Reckinger, N., Tang, X., Laszcz, A., Ratajczak, J., Halimaoui, A.: UHV fabrication of the ytterbium silicide as potential low Schottky barrier S/D contact material for n-type MOSFET. ECS Trans. 19, 339–344 (2009)CrossRefGoogle Scholar
  66. 66.
    Ghibaudo, G.: New method for the extraction of MOSFET parameters. Electron. Lett. 24, 543–545 (1988)CrossRefGoogle Scholar
  67. 67.
    Chang, L., Ieong, M., Yang, M.: CMOS circuit performance enhancement by surface orientation optimization. IEEE Trans. Electron. Devices 51, 1621–1627 (2004)CrossRefGoogle Scholar
  68. 68.
    Lecestre, A., Dubois, E., Villaret, A., Coronel, P., Skotnicki, T., Delille, D., Maurice, C., Troadec, D.: Synthesis and characterization of crystalline silicon ribbons on insulator using catalytic vapor–liquid–solid growth inside a cavity. Proc of the sixth workshop of the Thermatic Network on Silicon–On–Insulator Tecnology, Devices and Circuits, EUROSOI’10 (2010)Google Scholar

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© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • A. Lecestre
    • 1
    • 2
  • E. Dubois
    • 1
    Email author
  • A. Villaret
    • 2
  • T. Skotnicki
    • 2
  • P. Coronel
    • 3
  • G. Patriarche
    • 4
  • C. Maurice
    • 5
  1. 1.Institut d’Electronique, de Microélectronique et de NanotechnologieIEMN-CNRSVilleneuve d’AscqFrance
  2. 2.STMicroelectronicsCrolles CedexFrance
  3. 3.CEA-LITENGrenobleFrance
  4. 4.Laboratoire de Photonique et de NanostructuresLPN-CNRSMarcoussisFrance
  5. 5.Ecole des MinesCentre SMS, PECM-UMR CNRS 5146St EtienneFrance

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