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Confined and Guided Vapor–Liquid–Solid Catalytic Growth of Silicon Nanoribbons: From Nanowires to Structured Silicon-on-Insulator Layers

  • A. Lecestre
  • E. DuboisEmail author
  • A. Villaret
  • T. Skotnicki
  • P. Coronel
  • G. Patriarche
  • C. Maurice
Chapter
  • 1.7k Downloads
Part of the Engineering Materials book series (ENG.MAT.)

Abstract

The stacking of crystal semiconductor thin films alternated with dielectric layers continuously arouses a sustained interest for its utility in three-dimensional (3D) integration of metal-oxide-semiconductor field-effect transistor (MOSFET). However, the growth of crystalline silicon without resorting to epitaxial growth from a crystal seed still constitutes an unresolved challenge. Although many different techniques ranging from solid-phase crystallization to thin-film bonding constitutes possible solutions with their respective advantages and weaknesses, little attention has been paid so far to the adaptation of a technique widely used for producing semiconductor nanowires, namely, the vapor–liquid–solid (VLS) catalytic growth. The basic idea developed in this chapter is to control VLS growth for synthesizing local silicon-on-insulator (SOI) layers at reduced thermal budget. Confined VLS growth is therefore proposed to produce single crystalline silicon (c-Si) film over an amorphous oxide layer, without crystalline seeding. It is demonstrated that VLS growth in the spatial confinement of a cavity produces nanometer-thick c-Si ribbons over a micron area scale with a well controlled localization. The nature of grown silicon layers is characterized by SEM (Scanning Electron Microscopy), EBSD (Electron Backscattered Diffraction) and STEM (Scanning Transmission Electron Microscopy) to analyze its crystallinity and to check the impact of the confining cavity walls on the purity of grown silicon. Beyond the in-depth structural analysis of VLS grown nanoribbons, simple back-gated MOSFET structures have been fabricated and electrically characterized to extract transport properties. The obtained hole mobility of 53 cms−1 V−1 constitutes an excellent compromise for a processing temperature less or equal to 500°C.

Keywords

Twin Boundary Electron Backscatter Diffraction Amorphous Substrate Transmission Electron Microscopy Characterization Wide Cavity 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • A. Lecestre
    • 1
    • 2
  • E. Dubois
    • 1
    Email author
  • A. Villaret
    • 2
  • T. Skotnicki
    • 2
  • P. Coronel
    • 3
  • G. Patriarche
    • 4
  • C. Maurice
    • 5
  1. 1.Institut d’Electronique, de Microélectronique et de NanotechnologieIEMN-CNRSVilleneuve d’AscqFrance
  2. 2.STMicroelectronicsCrolles CedexFrance
  3. 3.CEA-LITENGrenobleFrance
  4. 4.Laboratoire de Photonique et de NanostructuresLPN-CNRSMarcoussisFrance
  5. 5.Ecole des MinesCentre SMS, PECM-UMR CNRS 5146St EtienneFrance

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