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Floating-Body SOI Memory: The Scaling Tournament

  • M. BawedinEmail author
  • S. Cristoloveanu
  • A. Hubert
  • K. H. Park
  • F. Martinez
Chapter
Part of the Engineering Materials book series (ENG.MAT.)

Abstract

In this paper, we present an overview of the typical device architectures of the single transistor capacitorless dynamic random access memory (1T-DRAM). This memory uses only one transistor and takes advantage of floating body effects in SOI and SOI-like devices. The principles of operation and key mechanisms for programming are described. The various approaches are compared in terms of architecture, performance and potential for aggressive scaling.

Keywords

Quantum Well Impact Ionization Bipolar Junction Transistor Drain Voltage Floating Body 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

Part of this work has been supported by the European Union programs EUROSOI+ and NANOSIL.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • M. Bawedin
    • 1
    • 2
    Email author
  • S. Cristoloveanu
    • 2
  • A. Hubert
    • 3
  • K. H. Park
    • 2
  • F. Martinez
    • 1
  1. 1.IES (UMR 5214)Université de Montpellier IIMontpellierFrance
  2. 2.IMEP-LAHC (UMR 5130)Grenoble INP MinatecGrenoble Cedex 1France
  3. 3.CEA-LETIMinatecGrenoble Cedex 9France

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