Abstract
A review of the main mobility results obtained in short channel devices (here GAA/DG, FD-SOI MOSFETs and FinFETs) are discussed for better understanding their transport limitations and performances. Regarding short channel GAA, FD-SOI and FinFET MOS devices, it has been shown that the mobility is strongly degraded at small gate length, whatever the architecture, the gate stack and the measurement method used. In particular, it has been found that, for FD-SOI, the mobility is more degraded at the top interface than at the bottom interface, revealing that defects are more numerous at the top channel region.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
References
Ghani, T., Armstrong, M., Auth, C., Bost, M., Charvat, P., Glass, G., Hoffmann, T., Johnson, K., Kenyon, C., Klaus, J., McIntyre, B., Mistry, K., Murth, A., Sandford, J., Silberstein, M., Sivakumar, S., Smith, P., Zawadzki, K., Thompson, S., Bohr, M.: A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors. In: IEEE Proceedings of IEDM, pp. 978–980 (2003)
Andrieu, F., Ernst, T., Lime, F., Rochette, F., Romanjek, K., Barraud, S., Ravit, C., Boeuf, F., Jurczak, M., Casse, M., Weber, O., Brevard, L., Reimbold, G., Ghibaudo, G., Deleonibus, S.: Experimental and comparative investigation of low and high field transport in substrate- and process-induced strained nanoscaled MOSFETs. In: IEEE/VLSI Symposium, pp. 176–178 (2005)
Wong, H.-S.P., Frank, D.J., Solomon, P.M.: Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length generation. In: IEEE Proceedings of IEDM, pp. 407–410 (1998)
Cros, A., Romanjek, K., Fleury, D., Harrison, S., Cerutti, R., Coronel, P., Dumont, B., Pouydebasque, A., Wacquez, R., Duriez, B., Gwoziecki, R., Boeuf, F., Brut, H., Ghibaudo, G., Skotnicki, T.: Unexpected mobility degradation for very short devices: a new challenge for CMOS scaling. In: IEEE Proceedings of IEDM, pp. 439–402 (2006)
Lochtefeld, A., Antoniadis, D.A.: Investigating the relationship between electron mobility and velocity in deeply scaled NMOS via mechanical stress. IEEE Electron. Device Lett. 22, 591–593 (2001)
Ghibaudo, G.: New method for the extraction of MOSFET parameters. Electron. Lett. 24, 543–545 (1988)
Romanjek, K., Andrieu, F., Ernst, T., Ghibaudo, G.: Improved split C-V method for effective mobility extraction in sub-0.1-μm Si MOSFETs. IEEE Electron. Device Lett. 25, 583–585 (2004)
Lime, F., Andrieu, F., Derix, J., Ghibaudo, G., Boeuf, F., Skotnicki, T.: Low temperature characterization of effective mobility in uniaxially and biaxially strained nMOSFETs. Solid State Electron. 50, 644–649 (2006)
Pappas, I., Ghibaudo, G., Dimitriadis, C.A., Fenouillet-Beranger, C.: Backscattering coefficient and drift-diffusion mobility extraction in short channel MOS devices. Solid State Electron. 53, 54–56 (2009)
Pham-Nguyen, L., Fenouillet-Beranger, C., Vandooren, A., Skotnicki, T., Ghibaudo, G., Cristoloveanu, S.: In situ comparison of Si/high-kappa and Si/SiO2 channel properties in SOI MOSFETs. IEEE Electron. Device Lett. 30, 1075–1077 (2009)
Bennamane, K., Boutchacha, T., Ghibaudo, G., Mouis, M., Collaert, N.: DC and low frequency noise characterization of FinFET devices. Solid State Electron. 53, 1263–1267 (2009)
Lundstrom, M.: On the mobility versus drain current relation for a nanoscale MOSFET. IEEE Electron. Device Lett. 22, 293–295 (2001)
Shur, M.S.: Low ballistic mobility in submicron HEMTs. IEEE Electron. Device Lett. 23, 511–513 (2002)
Yang, N., Henson, W.K., Hauser, J.R., Wortman, J.J.: Estimation of the effects of remote charge scattering on electron mobility of n-MOSFET’s with ultrathin gate oxides. IEEE Trans. Electron. Devices 47, 440–447 (2000)
Sah, C.T., Ning, T.H., Tschopp, L.L.: The scattering of electrons by surface oxide charges and by lattice vibrations at the silicon-silicon dioxide interface. Surf. Sci. 32, 561–575 (1972)
Sun, S.C., Plummer, J.D.: Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces. IEEE Trans. Electron. Devices 27, 1497–1508 (1980)
Denorme, S., Mathiot, D., Dollfus, P., Mouis, M.: 2-Dimensional modelling of the enhanced diffusion in thin base N-P-N bipolar transistors after lateral ion implantations. IEEE Trans. Electron. Devices 42, 523–527 (1995)
CEMES/CNRS: IPROS manual Monte Carlo simulation of ion implantation into real devices. Internal document, CEMES/CNRS (1994)
Erginsoy, C.: Neutral impurity scattering in semiconductors. Phys. Rev. 79, 1013–1014 (1950)
Ouisse, T., Physica, B.: Neutral impurity scattering with electron screening, vol. 270, pp. 262–271 (1999)
Acknowledgments
This work has been partially supported by European PULLNANO/FP6 integrated project and NANOSIL network of excellence.
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2011 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Ghibaudo, G. (2011). Mobility Characterization in Advanced FD-SOI CMOS Devices. In: Nazarov, A., Colinge, JP., Balestra, F., Raskin, JP., Gamiz, F., Lysenko, V. (eds) Semiconductor-On-Insulator Materials for Nanoelectronics Applications. Engineering Materials. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15868-1_17
Download citation
DOI: https://doi.org/10.1007/978-3-642-15868-1_17
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-15867-4
Online ISBN: 978-3-642-15868-1
eBook Packages: Chemistry and Materials ScienceChemistry and Material Science (R0)