Single Dopant and Single Electron Effects in CMOS Devices
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For the first time a state-of-the-art CMOS foundry (CEA-LETI-MINATEC) has been used to design silicon nanostructures with single or multiple gates dedicated to the study of single electron effects. The nanofabrication uses two e-beam lithography steps to define an active region formed by silicon-on-insulator (SOI) nanowires of cross section down to 20 nm × 10 nm and polysilicon gates of lengths down to 20 nm. The pitch at the gate level (distance between centers of the successive gates) is as small as 70 nm. Several technological splits (SOI thickness, channel doping, LDD doping, nitride spacer’s length, trimming of active layer) have been made to compare devices differing only by one crucial parameter. Several dozen of designs have been introduced in the e-beam data base to analyse the impact of key geometrical parameters. As a whole more than 40,000 samples have been fabricated and several hundreds of them have been studied electrically, mostly at low temperature. Some of them are described in this contribution.
KeywordsGate Voltage Silicon Nanowire Tunnel Barrier Coulomb Blockade Single Electron Transistor
Work done in collaboration with the AFSiD Partners. The research leading to these results has received funding from the European Community’s seventh Framework (FP7 2007/2013) under the Grant Agreement Nr:214989. The samples subject of this work have been designed and made by the AFSID Project Partners http://www.afsid.eu.
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