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Single Dopant and Single Electron Effects in CMOS Devices

  • M. SanquerEmail author
  • X. Jehl
  • M. Pierre
  • B. Roche
  • M. Vinet
  • R. Wacquez
Chapter
Part of the Engineering Materials book series (ENG.MAT.)

Abstract

For the first time a state-of-the-art CMOS foundry (CEA-LETI-MINATEC) has been used to design silicon nanostructures with single or multiple gates dedicated to the study of single electron effects. The nanofabrication uses two e-beam lithography steps to define an active region formed by silicon-on-insulator (SOI) nanowires of cross section down to 20 nm × 10 nm and polysilicon gates of lengths down to 20 nm. The pitch at the gate level (distance between centers of the successive gates) is as small as 70 nm. Several technological splits (SOI thickness, channel doping, LDD doping, nitride spacer’s length, trimming of active layer) have been made to compare devices differing only by one crucial parameter. Several dozen of designs have been introduced in the e-beam data base to analyse the impact of key geometrical parameters. As a whole more than 40,000 samples have been fabricated and several hundreds of them have been studied electrically, mostly at low temperature. Some of them are described in this contribution.

Keywords

Gate Voltage Silicon Nanowire Tunnel Barrier Coulomb Blockade Single Electron Transistor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

Work done in collaboration with the AFSiD Partners. The research leading to these results has received funding from the European Community’s seventh Framework (FP7 2007/2013) under the Grant Agreement Nr:214989. The samples subject of this work have been designed and made by the AFSID Project Partners http://www.afsid.eu.

References

  1. 1.
    Hofheinz, M., Jehl, X., et al.: A simple and controlled single electron transistor based on doping modulation in silicon nanowires. Appl. Phys. Lett. 89, 143504–143506 (2006)CrossRefGoogle Scholar
  2. 2.
    Hofheinz, M., Jehl, X., et al.: Capacitance enhancement in Coulomb blockade tunnel barriers. Phys. Rev. B 75, 235301–235304 (2007)CrossRefGoogle Scholar
  3. 3.
    Jehl, X., Sanquer, M., et al.: Nanoelectronics with CMOS transistors: electrostatic and quantum effects. In: Lévy L. P. (ed.) Special Issue: on Nanotechnology in France II: C’NANO Rhône-Alpes Guest. Lévy Int. J. Nanotechnol. 7, 4–8 (2010)Google Scholar
  4. 4.
    Deleonibus, S., et al.: Physical and technological limitations of NanoCMOS devices to the end of the roadmap and beyond. In: Deleonibus, S. (ed.) Electronic Device Architectures for the Nano-CMOS Era. Pan Stanford Publishing, Singapore (2009)Google Scholar
  5. 5.
    Hofheinz, M., Jehl, X., et al.: Individual charge traps in silicon nanowires: Measurements of location, spin and occupation number by Coulomb blockade spectroscopy. Eur. Phys. J. B 54, 299–307 (2006)CrossRefGoogle Scholar
  6. 6.
    Boehm, M., Hofheinz, M., et al.: Size scaling of the addition spectra in silicon quantum dots. Phys. Rev. B 71, 033305–033308 (2005)CrossRefGoogle Scholar
  7. 7.
    Ono, Y., Fujiwara, A., et al.: Manipulation and detection of single electrons for future information processing. J. Appl. Phys. 97, 031101–031103 (2005)CrossRefGoogle Scholar
  8. 8.
    Pierre, M., Wacquez, R., et al.: Compact silicon double and triple dots realized with only two gates. Appl. Phys. Lett. 95, 242107–242109 (2009)CrossRefGoogle Scholar
  9. 9.
    Zimmerman, N.M., Simonds, B.J., et al.: Charge offset stability in tunable-barrier Si single-electron tunneling devices. Appl. Phys. Lett. 90, 033507–033509 (2007)CrossRefGoogle Scholar
  10. 10.
    Pierre, M., Jehl, X., et al.: Sample variability and time stability in scaled silicon nanowires. ULIS2009 proceedings. (2009). doi: 10.1109/ULIS.2009.4897583
  11. 11.
    Jehl, X., Sanquer, M., et al.: Random telegraph noise in ultimate MOSFETS at very low temperature in the subthreshold regime. J. Phys. 4(12), Pr3–Pr107 (2002)Google Scholar
  12. 12.
    Shin, S.J., Jeong, C.S., et al.: Enhanced quantum effects in an ultra-small coulomb blockaded. device operating at room-temperature. arXiv:1003.2112 (2010)Google Scholar
  13. 13.
    Gautier, J., Jehl, X., Sanquer, M.: Single electron devices and applications. In: Stanford Pan and World Scientific Publishing Corporation (ed.) Electronic Devices Architectures for the NANO-CMOS Era (2008)Google Scholar
  14. 14.
    Buehler, T.M., Chan, V., et al.: Controlled single electron transfer between Si:P dots. Appl. Phys. Lett. 88, 192101–192103 (2006)CrossRefGoogle Scholar
  15. 15.
    Lansbergen, G.P., Rahman, R., et al.: Gate-induced quantum-confinement transition of a single dopant atom in a silicon. FinFET. Nat. Phys. 4, 656–661 (2008)CrossRefGoogle Scholar
  16. 16.
    Pierre, M., Wacquez, R., et al.: Single donor ionization energies in a nanoscale CMOS channel. Nat. Nanotechnol. 5, 133–135 (2009)CrossRefGoogle Scholar
  17. 17.
    Diarra, M., Niquet, Y.M., et al.: Ionization energy of donor and acceptor impurities in semiconductor nanowires: importance of dielectric confinement. Phys. Rev. B 75, 045301–045304 (2007)CrossRefGoogle Scholar
  18. 18.
    Wacquez, R., Vinet, M., et al.: Single dopant impact on electrical characteristics of SOI NMOSFETs with effective lengths down to 10 nm. Invited contribution VLSI Symposium 2010. (2010)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • M. Sanquer
    • 1
    Email author
  • X. Jehl
    • 1
  • M. Pierre
    • 1
  • B. Roche
    • 1
  • M. Vinet
    • 2
  • R. Wacquez
    • 1
  1. 1.INAC-SPSMS-LaTEQSCEA-GrenobleGrenobleFrance
  2. 2.CEA-LETI-MINATECCEA-GrenobleGrenobleFrance

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