Abstract
A new differential CMOS dynamic comparator using positive feedback with less power dissipation, less offset has been proposed. For the performance verification, the design was simulated in CADENCE GPDK 90nm CMOS Technology at 1.8Vsupply voltage. Nearly 18mV Offset Voltage, power dissipation 2.564mW, speed 2.812GHZ, propagation delay 0.3556ns is easily achieved with the proposed structure. Inputs are reconfigured from typical differential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta-stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the differential pairs.
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Velagaleti, S., Gorpuni, P., Mahapatra, K.K. (2010). A Novel High Speed Dynamic Comparator Using Positive Feedback with Low Power Dissipation and Low Offset. In: Das, V.V., Vijaykumar, R. (eds) Information and Communication Technologies. ICT 2010. Communications in Computer and Information Science, vol 101. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15766-0_7
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DOI: https://doi.org/10.1007/978-3-642-15766-0_7
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-15765-3
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