Abstract
Interpolation is the main bottleneck in AVS real-time high definition video encoder for its high memory bandwidth and large calculation complexity caused by the new coding features of variable block size and 4-tap filter. In this paper, a high performance VLSI architecture of interpolation supporting AVS Baseline@L4 is presented. Vertical redundant data reuse, horizontal redundant data reuse and sub-pixel data reuse schemes are presented to reduce memory bandwidth and processing cycle. The separated 1-D interpolation filters are used to improve throughput and hardware utilization. The proposed design is implemented on FPGA with operating frequency of 150MHz and can support 1080p (1920×1080)/30fps AVS real-time encoder. It is a useful intellectual property design for real-time high definition video application.
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References
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Guanghua, C., Anqi, W., Dengji, H., Shiwei, M., Weimin, Z. (2010). VLSI Implementation of Sub-pixel Interpolator for AVS Encoder. In: Li, K., Fei, M., Jia, L., Irwin, G.W. (eds) Life System Modeling and Intelligent Computing. ICSEE LSMS 2010 2010. Lecture Notes in Computer Science, vol 6329. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15597-0_39
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DOI: https://doi.org/10.1007/978-3-642-15597-0_39
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-15596-3
Online ISBN: 978-3-642-15597-0
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