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The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes

  • Daisuke Suzuki
  • Koichi Shimizu
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6225)

Abstract

In this paper we propose a new Delay-PUF architecture that is expected to solve the current problem of Delay-PUF that it is easy to predict the relation between delay information and generated information. Our architecture exploits glitches that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We call this architecture Glitch PUF. In this paper, we present a concrete structure of Glitch PUF. We then show the evaluation results on the randomness and statistical properties of Glitch PUF. In addition, we present a simple scheme to evaluate Delay-PUFs by simulation at the design stage. We show the consistency of the evaluation results for real chips and those by simulation for Glitch PUF.

Keywords

Trusted Platform Module Digital Right Management Secrecy Rate Physical Unclonable Function Delay Information 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Daisuke Suzuki
    • 1
    • 2
  • Koichi Shimizu
    • 1
  1. 1.Information Technology R&D CenterMitsubishi Electric Corporation 
  2. 2.Graduate School of Environmental and Information SciencesYokohama National University 

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