Abstract
In this paper we propose a new Delay-PUF architecture that is expected to solve the current problem of Delay-PUF that it is easy to predict the relation between delay information and generated information. Our architecture exploits glitches that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We call this architecture Glitch PUF. In this paper, we present a concrete structure of Glitch PUF. We then show the evaluation results on the randomness and statistical properties of Glitch PUF. In addition, we present a simple scheme to evaluate Delay-PUFs by simulation at the design stage. We show the consistency of the evaluation results for real chips and those by simulation for Glitch PUF.
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Keywords
- Trusted Platform Module
- Digital Right Management
- Secrecy Rate
- Physical Unclonable Function
- Delay Information
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Suzuki, D., Shimizu, K. (2010). The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes . In: Mangard, S., Standaert, FX. (eds) Cryptographic Hardware and Embedded Systems, CHES 2010. CHES 2010. Lecture Notes in Computer Science, vol 6225. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-15031-9_25
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DOI: https://doi.org/10.1007/978-3-642-15031-9_25
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