Abstract
In this chapter, architecture of a typical hardware (HW) CABAC encoder is illustrated. The design methodology of a SoC (System-on-Chip) based entropy coder is first presented. Based on the design methodology, hardware/software (HW/SW) functional partitioning of CABAC encoder function is carried out to decide which functions are to be designed in HW and which functions are to be processed on host processor. Furthermore, the strategy of functional partitioning of HW encoder is applied, and the top-level function blocks and encoding flow of the encoder are introduced. In the subsequent sections, design details of major functional blocks are presented including binarization and bin packet generation and binary arithmetic coding (BAC). Finally, additional functions supported by the encoder including context model initialization, RDO function support in BAC are discussed.
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References
Le TM, Tian XH, Ho BL, Nankoo J, Lian Y (2006) System-on-chip design methodology for a statistical coder. In: Proceedings of 7th IEEE international workshop on rapid system prototyping, pp 82–90
Ho BL (2006) Performance and complexity analyses of H.264/AVC CABAC entropy coder. Master of engineering thesis, Department of Electrical and Computer Engineering, National University of Singapore
Sudharsanan S, Cohen A (2005) A hardware architecture for a context-adaptive binary arithmetic coder. In: Proceedings of SPIE embedded processors for multimedia and communications II, pp 104–112
Tian XH, Le TM, Jiang X, Lian Y (2008) A HW CABAC encoder with efficient context access scheme for H.264/AVC. In: Proceedings of IEEE international symposium on circuits and systems, pp 37–40
Osorio RR, Bruguera JD (2006) High-throughput architecture for H.264/AVC CABAC compression system. IEEE Trans Circuits Syst Video Technol 16(11):1376–1384
Kuo C-C, Lei S-F (2006) Design of a low power architecture for CABAC encoder in H.264. In: Proceedings of IEEE Asia Pacific conference on circuits and systems, pp 243–246
Li L, Song Y, Ikenaga T, Goto S (2006) A CABAC encoding core with dynamic pipeline for H.264/AVC main profile. In: Proceedings of IEEE Asia Pacific conference on circuits and systems, pp 760–763
Li M, Wu W (2006) A high throughput binary arithmetic coding engine for H.264/AVC. In: Proceedings of 8th international conference on solid-state and integrated circuit technology, pp 1914–1918
Osorio RR, Bruguera JD (2005) A new architecture for fast arithmetic coding in H.264 advanced video coder. In: Proceedings of 8th Euromicro conference on digital system design, pp 298–305
Shojania H, Sudharsanan S (2005) A high performance CABAC encoder. In: Proceedings of 3rd international IEEE-NEWCAS conference, pp 315–318
Osorio RR, Bruguera JD (2004) Arithmetic coding architecture for H.264/AVC CABAC compression system. In: Proceedings of Euromicro symposium on digital system design, pp 62–69
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© 2011 Springer-Verlag Berlin Heidelberg
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Tian, X., Le, T.M., Lian, Y. (2011). Design of a CABAC Encoder. In: Entropy Coders of the H.264/AVC Standard. Signals and Communication Technology. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-14703-6_4
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DOI: https://doi.org/10.1007/978-3-642-14703-6_4
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