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An Energy-Efficient FPGA-Based Packet Processing Framework

  • Dániel Horváth
  • Imre Bertalan
  • István Moldován
  • Tuan Anh Trinh
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6164)

Abstract

Modern packet processing hardware (e.g. IPv6-supported routers) demands high processing power, while it also should be power-efficient. In this paper we present an architecture for high-speed packet processing with a hierarchical chip-level power management that minimizes the energy consumption of the system. In particular, we present a modeling framework that provides an easy way to create new networking applications on an FPGA based board. The development environment consists of a modeling environment, where the new application is modeled in SystemC. Furthermore, our power management is modeled and tested against different traffic loads through extensive simulation analysis. Our results show that our proposed solution can help to reduce the energy consumption significantly in a wide range of traffic scenarios.

Keywords

energy management packet processing 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Dániel Horváth
    • 1
  • Imre Bertalan
    • 1
  • István Moldován
    • 1
  • Tuan Anh Trinh
    • 2
  1. 1.Inter-University Cooperative Research Centre for Telecommunications and InformaticsBudapest University of Technology and Economics 
  2. 2.Department of Telecommunications and MediainformaticsBudapest University of Technology and EconomicsBudapestHungary

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