Abstract
The progressive CMOS scaling drives the success of the global semiconductor industry. Detailed knowledge of transistor behaviour is necessary to overcome the many fundamental challenges faced by chip and systems designers. Grid technology has enabled the constantly increasing statistical variability introduced by discreteness of charge and matter to be examined in unprecedented detail. Over 200,000 transistors subject to random discrete dopants variability have been simulated, the results of which provide detailed insight into underlying physical processes. This paper outlines recent scientific results of the nanoCMOS project, and describes the way in which the scientific goals have been reflected in the grid-based e-infrastructure.
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References
Berkeley SPICE, http://bwrc.eecs.berkeley.edu/Classes/icbook/SPICE/
Ganga webpage, http://ganga.web.cern.ch/ganga/
Globus Security Infrastructure, http://www.globus.org/security
GridSAM — Grid Job Submission and Monitoring Web Service, http://gridsam.sourceforge.net/
International technology roadmap for semiconductors (2005), http://www.itrs.net/
Internet2 Shibboleth Architecture and Protocols, http://shibboleth.internet2.edu
Scotgrid webpage, http://www.scotgrid.ac.uk
Storage Resource Broker (SRB), http://www.sdsc.edu/srb/index.php
Alfieri, R., et al.: VOMS: an authorization system for virtual organizations. In: Fernández Rivera, F., Bubak, M., Gómez Tato, A., Doallo, R. (eds.) Across Grids 2003. LNCS, vol. 2970, pp. 33–40. Springer, Heidelberg (2004)
Ancona, M.G., Tiersten, H.F.: Macroscopic physics of the silicon inversion layer. Phys. Rev. B 35(15), 7959–7965 (1987)
Anjomshoaa, A., et al.: Job Submission Description Language (JSDL) Specification, Version 1.0 (2005), http://www.ogf.org/documents/GFD.56.pdf
Basney, J., Humphrey, M., Welch, V.: The MyProxy Online Credential Repository. Software Practice and Experience 35(9), 801–816 (2005)
Brown, A., Roy, G., Asenov, A.: Poly-Si-gate-related variability in decananometer MOSFETs with conventional architecture. IEEE Transactions on Electron Devices 54(11), 3056–3063 (2007)
Chadwick, D.W., Otenko, A., Ball, E.: Role-based Access Control with X.509 Attribute Certificates. IEEE Internet Computing 7(2), 62–69 (2003)
Edward, R., Zayas, R.: Andrew File System (AFSv3) Programmer’s Reference: Architectural Overview. Transarc Corporation, Pittsburgh (1991)
Frank, D.J., Taur, Y.: Design considerations for cmos near the limits of scaling. Solid State Electronics 46, 315–320 (2002)
Han, L., Sinnott, R.O., Asenov, A., et al.: Towards a Grid-enabled Simulation Framework for nanoCMOS Electronics. In: 3rd IEEE International Conference on e-Science, Bangalore, India (December 2007)
Heinrich, J.: A guide to the Pearson type IV distribution. Technical report, University of Pennsylvania (2004)
Inaba, S., Okano, K., et al.: High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide. IEEE Transactions on Electron Devices 49(12), 2263–2270 (2002)
Kohl, J.T., Neuman, B.C., T’so, T.Y.: The Evolution of the Kerberos Authentication System. Distributed Open Systems, 78–94 (1994)
Millar, C., Reid, D., et al.: Accurate statistical description of random dopant induced threshold voltage variability. IEEE Electron Device Letters 29(8) (2008)
Nassif, S., et al.: High performance CMOS variability in the 65 nm regime and beyond. IEDM Digest of Technical Papers, pp. 569–571 (2007)
Reid, D., Millar, C., et al.: Prediction of random dopant induced threshold voltage fluctuations in nanoCMOS transistors. In: SISPAD 2008 (2008) (in publication)
Roy, G., Brown, A., et al.: Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs. IEEE Transactions on Electron Devices 53(12), 3063–3070 (2006)
Sinnott, R.O., Asenov, A., et al.: Meeting the Design Challenges of nanoCMOS Electronics: An Introduction to an EPSRC pilot project. In: Proceedings of the UK e-Science All Hands Meeting (2006)
Sinnott, R.O., Asenov, A., et al.: Integrating Security Solutions to Support nanoCMOS Electronics Research. In: IEEE International Symposium on Parallel and Distributed Processing Systems with Applications, Sydney Australia (2008c)
Sinnott, R.O., Bayliss, C., et al.: Secure, Performance-Oriented Data Management for nanoCMOS Electronics. Submitted to e-Science 2008, Indiana, USA (December 2008d)
Sinnott, R.O., Chadwick, D., et al.: Advanced Security for Virtual Organizations: Exploring the Pros and Cons of Centralized vs Decentralized Security Models. In: 8th IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2008), Lyon, France (2008a)
Sinnott, R.O., Stewart, G., et al.: Supporting Security-oriented Collaborative nanoCMOS Electronics e-Research. In: International Conference on Computational Science, Krakow, Poland (2008b)
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Asenov, A. et al. (2010). Enabling Cutting-Edge Semiconductor Simulation through Grid Technology. In: Lirkov, I., Margenov, S., Waśniewski, J. (eds) Large-Scale Scientific Computing. LSSC 2009. Lecture Notes in Computer Science, vol 5910. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12535-5_43
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DOI: https://doi.org/10.1007/978-3-642-12535-5_43
Publisher Name: Springer, Berlin, Heidelberg
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