Skip to main content

Part of the book series: Studies in Computational Intelligence ((SCI,volume 294))

Abstract

This chapter presents the State-of-the-Art (SOA) in analog circuit design automation. First, the analog design flow is reviewed and the fundamental trends in design automation are discussed. Then, the existing approaches to circuit sizing are presented, outlining in each case their advantages and limitations. Next, a detailed discussion over the existing tools approaches is provided. Finally, conclusions concerning the specification and design of a new analog design automation methodology implementation will be drawn.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

eBook
USD 16.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book
USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. Horta, N.C.: Analog and mixed-Signal IC design automation: Synthesis and optimization overview. In: Proc. 5th Conference on Telecommunications, Tomar, Portugal (2005)

    Google Scholar 

  2. Martens, E., Gielen, G.: Classification of analog synthesis tools based on their architecture selection mechanisms. Integration, the VLSI Journal 41(2), 238–252 (2007)

    Article  Google Scholar 

  3. Degrauwe, M., et al.: IDAC: An interactive design tool for analog CMOS circuits. IEEE J. Solid-State Circuits 22, 1106–1115 (1987)

    Article  Google Scholar 

  4. Lourenço, N.: LAYGEN: Automatic layout generation of analog ICs, from a system to device level using both hierarchical template descriptions and intelligent computing techniques. Master thesis, Dept. Electrical and Computer Engineering, Instituto Superior Técnico, Portugal (2007)

    Google Scholar 

  5. Horta, N.C., Franca, J.E.: High-Level data conversion synthesis by symbolic methods. In: Proc. IEEE Int. Symposium on Circuits and Systems, vol. 4, pp. 802–805 (1996)

    Google Scholar 

  6. Horta, N.C.: Analogue and mixed-signal systems topologies exploration using symbolic methods. In: Proc. Analog Integrated Circuits and Signal Processing, vol. 31(2), pp. 161–176 (2002)

    Google Scholar 

  7. Harjani, R., Rutenbar, R.A., Carley, L.R.: OASYS: A framework for analog circuit synthesis. IEEE Trans. Computer-Aided Design 8, 1247–1265 (1989)

    Article  Google Scholar 

  8. El-Turky, F., Perry, E.: BLADES: An artificial intelligence approach to analog circuit design. IEEE Trans. Computer-Aided Design 8, 680–692 (1989)

    Article  Google Scholar 

  9. Koh, H.Y., Sequin, C.H., Gray, P.R.: OPASYN: A compiler for CMOS operational amplifiers. IEEE Trans. Computer-Aided Design 9(2), 113–125 (1990)

    Article  Google Scholar 

  10. Torralba, A., Chávez, J., Franquelo, L.G.: FASY: A fuzzy-logic based tool for analog synthesis. IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems 15(7), 705–715 (1996)

    Article  Google Scholar 

  11. Gielen, G., et al.: An analog module generator for mixed analog/digital ASIC design. Wiley Int. J. Circuit Theory Applications 23, 269–283 (1995)

    Article  Google Scholar 

  12. Kruiskamp, W., Leenaerts, D.: DARWIN: CMOS opamp synthesis by means of a genetic algorithm. In: Proc. ACM/IEEE Design Automation Conference, pp. 550–553 (1995)

    Google Scholar 

  13. Stehr, G., Pronath, M., Schenkel, F., Graeb, H., Antreich, K.: Initial sizing of analog integrated circuits by centering within topology given implicit specifications. In: Proc. IEEE International Conference on Computer-Aided Design, pp. 241–246 (2003)

    Google Scholar 

  14. Horta, N.C., Franca, J.E.: Algorithm-driven synthesis of data conversion architectures. IEEE Trans. Computer-Aided Design Integrated Circuits 16(10), 1116–1135 (1997)

    Article  Google Scholar 

  15. Konczykowska, A., Bon, M.: Structural synthesis and optimization of analog circuits symbolic analysis techniques. IEEE, Los Alamitos (1998)

    Google Scholar 

  16. Antoa, B.A., Brodersen, A.J.: ARCHGEN: Automated synthesis of analog systems. IEEE Trans. VLSI Systems 3(2), 231–244 (1995)

    Article  Google Scholar 

  17. Lohn, J.D., Colombano, S.P.: A circuit representation technique for automated circuit design. IEEE Trans. Evolutionary Computation 3(3), 205–219 (1999)

    Article  Google Scholar 

  18. Koza, J.R., Bennett, F.H., Andre, D., Keane, M.A., Dunlap, F.: Automated synthesis of analog electrical circuits by means of genetic programming. IEEE Trans. Evolutionary Computation 1(2), 109–128 (1997)

    Article  Google Scholar 

  19. Sripramong, T., Toumazou, C.: The invention of CMOS amplifiers using genetic programming and current-flow analysis. IEEE Trans. Comput. Aided Design Integrated Circuits 21(11), 1237–1252 (2002)

    Article  Google Scholar 

  20. Leenaerts, D., Gielen, G., Rutenbar, R.A.: CAD solutions and outstanding challenges for mixed-signal and RF IC design. In: Proc. IEEE/ACM International Conference on Computer Aided Design, pp. 270–277 (2001)

    Google Scholar 

  21. Aggarwal, V.: Analog circuit optimization using evolutionary algorithms and convex optimization. Master thesis, Dept. of Electrical Engineering and Computer Science, Massachusetts Institute of Technology (2007) http://web.mit.edu/varun_ag/www/msthesis.pdf (Accessed March 2009)

  22. Kuhn, J.: Analog module generators for silicon compilation. In: Proc. VLSI System Design, pp. 75–80 (1987)

    Google Scholar 

  23. Wolf, M., Kleine, U., Hosticka, B.J.: A novel analog module generator environment. In: Proc. European Conference on Design and Test, pp. 388–392 (1996)

    Google Scholar 

  24. Beenker, G., Conway, J., Schrooten, G., Slenter, A.: Analog CAD for consumer ICs. In: Huijsing, J., Plassche, R., Sansen, W. (eds.) Analog Circuit Design, pp. 347–367. Kluwer Academic Publishers, Norwell (1993)

    Google Scholar 

  25. Cohn, J., Garrod, D., Rutenbar, R.A., Carley, L.R.: KOAN/ANAGRAM II: New tools for device-level analog placement and routing. IEEE J. Solid-State Circuits 26, 330–342 (1991)

    Article  Google Scholar 

  26. Carley, L., Georges, G., Rutenbar, R.A., Sansen, W.: Synthesis tools for mixed-signal ICs: Progress on frontend and backend strategies. In: Proc. Design Automation Conference, vol. 33, pp. 298–303 (1996)

    Google Scholar 

  27. Lampaert, K., Gielen, G., Sansen, W.: A performance driven placement tool for analog integrated circuits. IEEE Journal of Solid-State Circuits 30, 773–780 (1995)

    Article  Google Scholar 

  28. Khademsameni, P., Syrzycki, M.: A tool for automated analog CMOS layout module generation and placement. In: Proc. IEEE Canadian Conference on Electrical and Computer Engineering, pp. 416–421 (2002)

    Google Scholar 

  29. Yılmaz, E., Dündar, G.: New Layout generator for analog CMOS circuits. In: Proc. 18th European Conference on Circuit Theory and Design, pp. 36–39 (2007)

    Google Scholar 

  30. Hartono, R., Jangkrajarng, N., Bhattacharya, S., Shi, C.: Automatic device layout generation for analog layout retargeting. In: Proc. International Conference on VLSI Design, vol. 36, pp. 457–462 (2005)

    Google Scholar 

  31. Lampaert, K., Gielen, G., Sansen, W.: Analog layout generation for performance and manufacturability. Kluwer Academic Publishers, Dordrecht (1999)

    Google Scholar 

  32. Jingnan, X., Vital, J., Horta, N.C.: A SKILLTM-based library for retargetable embedded analog cores. In: Proc. Design Automation and Test in Europe Conference and Exhibition, pp. 768–769 (2001)

    Google Scholar 

  33. Jingnan, X., Serras, J., Oliveira, M., Belo, R., Bugalho, M., Vital, J., Horta, N.C., Franca, J.: IC design automation from circuit level optimization to retargetable layout. In: Proc. 8th IEEE International Conference on Electronics, Circuits and Systems, vol. 1, pp. 95–98 (2001)

    Google Scholar 

  34. Rijmenants, I., Schwarz, Y.R., Litsios, J.B., Zinszner, R.: ILAC: An automated layout tool for CMOS circuits. IEEE Journal of Solid-State Circuits 24(2), 417–425 (1989)

    Article  Google Scholar 

  35. Lourenço, N., Horta, N.C.: LAYGEN – An evolutionary approach to automatic analog IC layout generation. In: Proc. IEEE Conf. on Electronics, Circuits and System, Tunisia (2005)

    Google Scholar 

  36. Lourenço, N., Vianello, M., Guilherme, J., Horta, N.C.: LAYGEN – Automatic layout generation of analog ICs from hierarchical template descriptions. In: Proc. IEEE Ph. D. Research in Microelectronics and Electronics, pp. 213–216 (2006)

    Google Scholar 

  37. Zhang, L., Kleine, U.: A genetic approach to analog module placement with simulated annealing. In: Proc. IEEE Int. Symposium on Circuits and Systems, vol. 1, pp. 345–348 (2002)

    Google Scholar 

  38. Handa, K., Kuga, S.: Polycell placement for analog LSI chip designs by genetic algorithms and tabu search. In: Proc. IEEE Conference on Evolutionary Computation, vol. 2, pp. 716–721 (1995)

    Google Scholar 

  39. Zhang, L., Kleine, U.: A novel analog layout synthesis tool. In: Proc. IEEE Int. Symposium on Circuits and Systems, vol. 5, pp. 101–104 (2004)

    Google Scholar 

  40. Jangkrajarng, N., Bhattacharya, S., Hartono, R., Shi, C.J.: IPRAIL: Intellectual property reuse based analog IC layout automation. Integration, the VLSI Journal 36(4), 237–262 (2003)

    Article  Google Scholar 

  41. Castro-Lopez, R., Fernandez, F.V., Guerra-Vinuesa, O., Vazquez, A.: Reuse Based Methodologies and Tools in the Design of Analog and Mixed-Signal Integrated Circuits. Springer, Heidelberg (2003)

    Google Scholar 

  42. Cory, W.: Layla: A VLSI Layout Language. In: Proc. 22nd ACM/IEEE Conference on Design Automation, pp. 245–251 (1985)

    Google Scholar 

  43. Nye, W., Riley, D.C., Sangiovanni-Vincentelli, A., Tits, A.L.: DELIGHT.SPICE: An optimization-based system for the design of integrated circuits. IEEE Trans. Computer-Aided Design 7(4), 501–519 (1998)

    Article  Google Scholar 

  44. Leme, C., Horta, N.C., Franca, J.E., Yufera, A., Rueda, A., Huertas, J.L., et al.: Flexible silicon compilation of charge redistribution data conversion systems. In: Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 403–406 (1991)

    Google Scholar 

  45. Horta, N.C., Franca, J.E., Leme, C.A.: Framework for architecture synthesis of data conversion systems employing binary-weighted capacitor arrays. In: Proc. IEEE Int. Symposium on Circuits and Systems, pp. 1789–1792 (1991)

    Google Scholar 

  46. Harvey, J.P., Elmasry, M.I., Leung, B.: STAIC: An interactive framework for synthesizing CMOS and BICMOS analog circuits. IEEE Trans. Computer-Aided Design 11(11), 1402–1417 (1992)

    Article  Google Scholar 

  47. Maulik, P.C., Carley, L.R.: Automating analog circuit design using constrained optimization techniques. In: Proc. IEEE Int. Conf. Computer-Aided Design, pp. 390–393 (1991)

    Google Scholar 

  48. Ochotta, E.S., Rutenbar, R.A., Carley, L.R.: Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. Computer- Aided Design 15(3), 273–294 (1996)

    Article  Google Scholar 

  49. Hershenson, M., Boyd, S., Lee, T.: GPCAD: A tool for CMOS op-amp synthesis. In: Proc. IEEE/ACM Int. Conf. Computer-Aided Design, pp. 296–303 (1998)

    Google Scholar 

  50. Hershenson, M.M., Boyd, S.P., Lee, T.H.: Optimal design of a CMOS Op-Amp via geometric programming. IEEE Trans. Computer-Aided Design 20(1), 1–21 (2001)

    Article  Google Scholar 

  51. Medeiro, F., Verdu, B.P., Vazquez, A.R., Huertas, J.L.: A vertically integrated tool for automated design of modulators. IEEE Journal of Solid-State Circuits 30(7) (1995)

    Google Scholar 

  52. Gielen, G., Wambacq, P., Sansen, W.: Symbolic analysis methods and applications for analog circuits: A tutorial overview. Proc. IEEE 82, 287–304 (1994)

    Article  Google Scholar 

  53. Wambacq, P., Fernandez, F.V., Gielen, G., Sansen, W., Rodriguez-Vazquez, A.: Efficient symbolic computation of approximated small signal characteristics. IEEE J. Solid-State Circuits 30, 327–330 (1995)

    Article  Google Scholar 

  54. Daems, W., Gielen, G., Sansen, W.: An efficient optimization–based technique to generate posynomial performance models for analog integrated circuits. In: Proc. 39th Design Automation Conference, pp. 431–436 (2002)

    Google Scholar 

  55. Medeiro, F., et al.: A Statistical optimization-based approach for automated sizing of analog cells. In: Proc. ACM/IEEE Int. Conf. Computer-Aided Design, pp. 594–597 (1994)

    Google Scholar 

  56. Phelps, R., Krasnicki, M., Rutenbar, R.A., Carley, L.R., Hellums, J.: ANACONDA: Simulation-based synthesis of analog circuits via stochastic pattern search. IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems 19(6), 703–717 (2000)

    Article  Google Scholar 

  57. Krasnicki, M., Phelps, R., Rutenbar, R.A., Carley, L.R.: MAELSTROM: Efficient simulation-based synthesis for custom analog cells. In: Proc. ACM/IEEE Design Automation Conference, pp. 945–950 (1999)

    Google Scholar 

  58. Liu, H., Singhee, A., Rutenbar, R.A., Carley, L.: Remembrance of circuits past: Macromodeling by data mining in large analog design spaces. In: Proc. Design Automation Conference, pp. 437–442 (2002)

    Google Scholar 

  59. Alpaydin, G., Balkir, S., Dundar, G.: An evolutionary approach to automatic synthesis of high-performance analog integrated circuits. IEEE Trans on Evol. Computation 7(3), 240–252 (2003)

    Article  Google Scholar 

  60. Bernardinis, F., Jordan, M.I., Sangiovanni-Vincentelli, A.: Support vector machines for analog circuit performance representation. In: Proc. Design Automation Conference, pp. 964–969 (2003)

    Google Scholar 

  61. Wolfe, G.A.: Performance macro-modeling techniques for fast analog circuit synthesis. Ph.D. dissertation, Dept. of Electrical and Computer Engineering and Computer Science, College of Engineering, University of Cincinnati, USA (1999)

    Google Scholar 

  62. Synopsys Inc.: Products and solutions-HSIM, PowerMill, NanoSim (2009), http://www.synopsys.com (Accessed March 2009)

  63. EEDesign, Synopsys acquires ADA for analog boost (2009), http://www.eetimes.com/ (Accessed March 2009)

  64. Synopsys Inc.: Circuit Explorer - analysis, optimization & trade-off (2009), http://www.synopsys.com (Accessed March 2009)

  65. Cadence Inc, Products: Composer, Virtuoso, DIVA, NeoCircuit, NeoCell, UltraSim, NcSim (2009), http://www.cadence.com (Accessed March 2009)

  66. Toumazou, C., Makris, C.: Analog IC design automation: Part I - Automated circuit generation: New concepts and methods. IEEE Trans. Computer-Aided Design 14, 218–238 (1995)

    Article  Google Scholar 

  67. Makris, C., Toumazou, C.: ISAID: Qualitative reasoning and trade-off analysis in analog IC design automation. In: Proc. IEEE Int. Symposium on Circuits and Systems, pp. 2364–2367 (1992)

    Google Scholar 

  68. Toumazou, C., Makris, C.A., Berrah, C.M.: ISAID - a methodology for automated analog IC design. In: Proc. IEEE Int. Symposium on Circuits and Systems, vol. 1, pp. 531–535 (1990)

    Google Scholar 

  69. Barros, M., Neves, G., Guilherme, J., Horta, N.C.: Enhanced genetic algorithm kernel applied to a circuit-level optimization E-Design environment. In: Proc. 10th IEEE International Conference on Electronics, Circuits and Systems, pp. 1046–1049 (2003)

    Google Scholar 

  70. Barros, M., Neves, G., Guilherme, J., Horta, N.C.: Analog Circuits Optimization based on Evolutionary Computation Techniques. Integration, the VLSI Journal 43(1), 136–155 (2010)

    Article  Google Scholar 

Download references

Authors

Rights and permissions

Reprints and permissions

Copyright information

© 2010 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Barros, M.F.M., Guilherme, J.M.C., Horta, N.C.G. (2010). State-of-the-Art on Analog Design Automation. In: Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques. Studies in Computational Intelligence, vol 294. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12346-7_2

Download citation

  • DOI: https://doi.org/10.1007/978-3-642-12346-7_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-12345-0

  • Online ISBN: 978-3-642-12346-7

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics