Abstract
This paper presents a hierarchical model-order reduction (HMOR) flow, where the linear parts of a hierarchically defined circuits are divided into independently reducable subcircuits. The impact of the hierarchical structure and circuit partitioning on two MOR methods is discussed and some simulation results are presented.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Lee, Y.M., Chen, C.C.P.: Hierarchical model order reduction for signal-integrity interconnect synthesis. In: Proceedings of the 11th Great Lakes symposium on VLSI, pp. 109–114 (2001)
Lee, Y.M., Cao, Y., Chen, T.H., Wang, J.M., Chen, C.C.P.: HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for rlck power delivery. IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems 24, 797–806 (2005)
Karypis, G., Kumar, V.: hMETIS, a hypergraph partitioning package version 1.5.3
Karypis, G., Kumar, V.: METIS, a software package for partitioning unstructured graphs, partitioning meshes, and computing fill-reducing orderings of sparse matrices version 4.0
Odabasioglu, A., Celik, M., Pileggi, L.T.: PRIMA: passive reduced-order interconnect macromodeling algorithm. IEEE Transactions on Computer-Aided design of Integrated Circuits and Systems 17, 645–654 (1998)
Liao, H., Dai, W.W.M.: Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels. In: Digest of Technical Papers of IEEE/ACM International Conference on Computer Aided Design, pp. 704–709 (1995)
Miettinen, P., Honkala, M., Roos, J.: Partioning-based RL-in-RL-out MOR method. In: SCEE 2008 Book of Abstracts, pp. 119–120 (2008)
Rommes, J., Lenaers, P., Schilders, W.H.A.: Model order reduction for large resistance networks. In: SCEE 2008 Book of Abstracts, pp. 27–28 (2008)
Palenius, T., Roos, J.: Comparison of reduced-order interconnect macromodels for time-domain simulation. IEEE Transactions on Microwave Theory and Techniques 52(9), 2240–2250 (2004)
Matsumoto, Y., Tanji, Y., Tanaka, M.: Efficient SPICE-netlist representation of reduced-order interconnect model. In: Proceedings of ECCTD’01, vol. 2, pp. 145–148. Espoo, Finland (2001)
Miettinen, P., Honkala, M., Roos, J., Neff, C., Basermann, A.: Study and development of an efficient RC-in–RC-out mor method. In: Proceedings of ICECS 2008, pp. 1277–1280 (2008)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Honkala, M., Miettinen, P., Roos, J., Neff, C. (2010). Hierarchical Model-Order Reduction Flow. In: Roos, J., Costa, L. (eds) Scientific Computing in Electrical Engineering SCEE 2008. Mathematics in Industry(), vol 14. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12294-1_66
Download citation
DOI: https://doi.org/10.1007/978-3-642-12294-1_66
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-12293-4
Online ISBN: 978-3-642-12294-1
eBook Packages: Mathematics and StatisticsMathematics and Statistics (R0)