Abstract
The burden of solving inner equations in compact models of semiconductor devices (such as transistors) is often shifted to the host circuit simulator. Schur complement techniques for local handling of these equations may help to reduce the size of the model stamp, which – depending on the host simulator – may have a positive impact on CPU time and memory needs. Some practical aspects of applying these concepts in compact modeling are discussed. A formulation is presented which accounts for the specific way of model evaluation in circuit simulation. It can be realized in a standard code for flat model evaluation by adding a software shell around the model core function itself.
First tests with an advanced high voltage MOS model demonstrate the feasibility of this approach in terms of accuracy, iterations and runtimes.
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Feldmann, U., Miyake, M., Kajiwara, T., Miura-Mattausch, M. (2010). On Local Handling of Inner Equations in Compact Models. In: Roos, J., Costa, L. (eds) Scientific Computing in Electrical Engineering SCEE 2008. Mathematics in Industry(), vol 14. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-12294-1_19
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DOI: https://doi.org/10.1007/978-3-642-12294-1_19
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