An Efficient Hardware Architecture from C Program with Memory Access to Hardware
To improve the performance and power-consumption of the system-on-chip (SoC), the software processes are often converted to the hardware. However, to extract the performance of the hardware as much as possible, the memory access must be improved. In addition, the development period of the hardware has to be reduced because the life-cycle of SoC is commonly short. This paper proposes a design-level hardware architecture (semi-programmable hardware: SPHW) which is inserted onto the pass from C to hardware. On the SPHW, the memory accesses and buffers are realized by the software programming and parameters respectively. By using the SPHW you can easily develop the data processing hardware containing the efficient memory access controller at C-level abstraction. Compared with the conventional cases, the SPHW can reduce the development time significantly. The experimental result also shows that you can employ the SPHW as the final product if the memory access latency is hidden enough.
KeywordsDiscrete Wavelet Transform Memory Access Ring Register Hardware Architecture Hardware Description Language
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- 1.Agility Design Solutions Inc.: Handel-C Language Reference Manual RM-1003-4.4. Agility (2007)Google Scholar
- 4.Lau, D., Pritchard, O., Molson, P.: Automated Generation of Hardware Accelerators with Direct Memory Access from ANSI/ISO Standard C Functions. In: IEEE Symp. on Field-Programmable Custom Computing Machines, pp. 45–56 (2006)Google Scholar
- 6.Mitrionics: Mitrion Users’Guide 1.5.0-001. Mitrionics (2008)Google Scholar
- 7.NIST: Federal Information Processing Standard Publication 197, Advanced encryption standard (AES) (2001), http://csrc.nist.gov/publications/fips/fips197/fips197.pdf
- 8.Park, J., Diniz, P.C.: Synthesis of pipelined memory access controllers for streamed data applications on FPGA-based computing engines. In: Proc. of Intl. Symp. on Systems Synthesis, October 2001, pp. 221–226 (2001)Google Scholar
- 9.Pellerin, D., Thibault, S.: Practical FPGA Programming in C. Prentice-Hall, Englewood Cliffs (2005)Google Scholar
- 11.Xilinx: ML401/ML402/ML403 Evaluation Platform User Guide. Xilinx (2006)Google Scholar
- 12.Yamawaki, A., Morita, K., Iwane, M.: An FPGA Implementation of a DWT with 5/3 Filter Using Semi-Programmable Hardware. In: Proc. of the Asia Pacific Conference on Circuits and Systems, pp. 709–712 (2008)Google Scholar
- 13.Yamawaki, A., Serikawa, S., Iwane, M.: An Efficient Comparative Evaluation to Buffering Methods for Window-based Image Processing Using Semi-programmable Hardware. In: Proc. of the International Conference on Engineering of Reconfigurable Systems & Algorithms, pp. 233–239 (2009)Google Scholar
- 14.Yu, H., Leeser, M.: Optimizing data intensive window-based image processing on reconfigurable hardware boards. In: Proc. of Workshop on Signal Processing Systems Design and Implementation, November 2005, pp. 491–496 (2005)Google Scholar