Abstract
In this paper we present a new transistor sizing methodology called Free Power Recovery (FPR) for low power circuit design. The objective of this methodology is to minimize the total power of a circuit by accounting for node switching activities and leakage duty cycles (LDC). The methodology has been incorporated into the EinsTuner circuit tuning tool. EinsTuner automates the tuning process using state-of-the-art non-linear optimization solvers and fast circuit simulators. Node switching activities and LDC are integrated into the EinsTuner framework as parameter inputs to the FPR tuning mode. In FPR mode, the power is minimized using gate width reduction with respect to power properties of the node. The FPR methodology is evaluated on next generation microprocessor circuit designs. Power reduction results are compared with the results from the existing EinsTuner tuning methodology. The results show improvement in power reduction with the FPR optimization mode.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Horowitz, M., Stark, D., Alon, E.: Digital Circuit Design Trends. IEEE Journal of Solid-State Circuits 43(4), 757–761 (2008)
Oklobdzija, V.G., Krishnamurthy, R.K.: High-Performance Energy-Efficient Microprocessor Design. Series on Integrated Circuits and Systems. Springer-Verlag New York, Inc., Secaucus (2006)
Conn, A.R., Elfadel, I.M., Molzen, W.W., O’Brien, P.R., Strenski, P.N., Visweswariah, C., Whan, C.B.: Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation. In: DAC, pp. 452–459 (1999)
Berridge, R., et al.: IBM POWER6 Microprocessor Physical Design and Design Methodology. IBM Journal of Research and Development 51(6), 685–714 (2007)
Narendra, S., De, V., Antoniadis, D., Chandrakasan, A., Borkar, S.: Scaling of Stack Effect and its Application for Leakage Reduction. In: ISLPED 2001: Proceedings of the 2001 International Symposium on Low Power Electronics and Design, pp. 195–200. ACM, New York (2001)
BSIM 4.2.1 MOSFET Model: User’s Manual, Dept. of EECS, University of California, Berkeley, CA, USA (2002)
Wächter, A., Visweswariah, C., Conn, A.R.: Large-Scale Nonlinear Optimization in Circuit Tuning. Future Generation Computer Syst. 21(8), 1251–1262 (2005)
Rao, V.B., Soreff, J.P., Brodnax, T.B., Mains, R.E.: EinsTLT: Transistor-Level Timing with EinsTimer. In: Proceedings of the ACM/IEEE 1999 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (Tau 1999), pp. 1–6 (1999)
Bard, K., et al.: Transistor-Level Tools for High-End Processor Custom Circuit Design at IBM. Proceedings of the IEEE, invited paper (March 2007)
Neely, J.S., et al.: CPAM: A Common Power Analysis Methodology for High-Performance VLSI Design. In: IEEE Conf. Electrical Performance of Electronic Packaging, pp. 303–306. IEEE Press, Los Alamitos (2000)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2010 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Vratonjić, M. et al. (2010). A New Methodology for Power-Aware Transistor Sizing: Free Power Recovery (FPR). In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_35
Download citation
DOI: https://doi.org/10.1007/978-3-642-11802-9_35
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11801-2
Online ISBN: 978-3-642-11802-9
eBook Packages: Computer ScienceComputer Science (R0)