Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates

Abstract

This paper proposes a new approach for the analysis of the power consumption at the logic level of complex static CMOS gates. A new methodology for the capacitance modeling is described, which considers a mathematic model of equivalent concentrated capacitance at each external node of the gate. To generate this model, all the possible combinations of input vectors transitions and their capacitive effects are analyzed. A set of complex gates is modeled and the dissipated power is estimated with 100 input vectors. The results are compared with electric level simulation, using the Hspice tool of the Synopsys, and logic level, with Prime Power. A maximum error of 6.7% for a complex logic gate (OAI321) is found. Furthermore, to validate the method, power estimation of circuits composed essentially of complex gates was obtained and the maximum error found in this case was 6.2%. The main advantage of the method is the estimation time, which can be up to 160 times faster.