Abstract
This work presents a low-power dual-edge triggered static scanable flip-flop that uses reduced swing-clock and -data to manage dynamic power. The circuit employs clock- and power-gating during idle mode to eliminate dynamic power and reduce static power, while retaining circuit’s state. The static structure of the circuit makes it feasible to be employed in variable frequency power control designs. HSPICE post-layout simulation conducted for 90nm CMOS technology showed that in terms of power-delay product, device count, and leakage power the proposed design is comparable to other high performance static flip-flops.
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Karimiyan, H., Sayedi, S.M., Saidi, H. (2010). Low-Power Dual-Edge Triggered State Retention Scan Flip-Flop. In: Monteiro, J., van Leuken, R. (eds) Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2009. Lecture Notes in Computer Science, vol 5953. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-11802-9_20
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DOI: https://doi.org/10.1007/978-3-642-11802-9_20
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-11801-2
Online ISBN: 978-3-642-11802-9
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