Variability in Advanced Nanometer Technologies: Challenges and Solutions

Abstract

As process parameter dimensions continue to scale down, the gap between the designed layout and what is really manufactured on silicon is increasing. Due to the difficulty in process control in advanced nanometer technologies, manufacturing-induced variations are growing both in number and as a percentage of device feature sizes, and a deep understanding of the different sources of variation, along with their characterization and modeling, has become mandatory.

Furthermore, process variability makes the prediction of digital circuit performance an extremely challenging task. Traditionally, the methodology adopted to determine the performance spread of a design in presence of variability is to run multiple Static Timing Analyses at different process corners, where standard cells and interconnects have the worst/best combinations of delay. Unfortunately, as the number of variability sources increases, the corner-based method is becoming computationally very expensive. Moreover, with a larger parameter spread this approach results in overly conservative and suboptimal designs, leaving most of the advantages offered by the new technologies on the table. Statistical Static Timing Analysis (SSTA) is a promising approach to deal with nanometer process variations, especially the intra-die variations that cannot be handled properly by existing corner-based techniques, in the digital design flow.

Finally, the complexity and the impact of the variability problem on design productivity and profitability require innovative design solutions at the circuit and architectural level, and some of the most promising techniques for variability-aware design will be presented.