Robust Low Power Embedded SRAM Design: From System to Memory Cell

Abstract

Low power memories continue to be an important topic for low power digital design, especially in light of the recent focus on green products. Voltage scaling for some time was a natural part of technology scaling, which automatically resulted in power reduction. For sub-100nm technologies it has been difficult to reduce active power consumption for SRAMs, because the amount of memory in digital ICs is still increasing and the memory bit cell does not allow a lower supply voltage without a severe area penalty. However, voltage scaling is not a goal in itself, and a variety of techniques exist to achieve low power. This paper gives an overview of the trends in technology scaling and its impact on low power memory design. The most important techniques that are used to make low power SRAM are discussed, and system level considerations are given, including trade-offs on the selection of SRAM and DRAM. For advanced technologies, SRAM variability is an important topic. Lowering the supply voltage to save power increases the sensitivity of SRAM to variability and reduces its robustness. Simulation approaches used to guarantee high yield even for large amounts of SRAM are discussed. A combination of these methods and techniques helps to achieve low power, yet robust systems.