Abstract
Buffered crossbar switches are special crossbar switches with each crosspoint equipped with a small exclusive buffer. The crosspoint buffers decouple input ports and output ports, and simplify switch scheduling. In this paper, we propose a scheduling algorithm called Fair and Localized Asynchronous Packet Scheduling (FLAPS) for buffered crossbar switches, to provide tight performance guarantees. FLAPS needs no speedup for the crossbar and handles variable length packets without segmentation and reassembly (SAR). With FLAPS, each input port and output port independently make scheduling decisions and rely on only local queue statuses. We theoretically show that a crosspoint buffer size of 4L is sufficient for FLAPS to avoid buffer overflow, where L is the maximum packet length. In addition, we prove that FLAPS achieves strong stability, and provides bounded delay guarantees. Finally, we present simulation data to verify the analytical results.
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References
Kurose, J., Ross, K.: Computer networking: a top-down approach, 4th edn. Addison Wesley, Reading (2007)
McKeown, N.: A fast switched backplane for a gigabit switched router. Business Communications Review 27(12) (1997)
Katevenis, M., Passas, G.: Variable-size multipacket segments in buffered crossbar (CICQ) architectures. In: IEEE ICC 2005, Seoul, Korea (May 2005)
Kornaros, G.: BCB: a buffered crossBar switch fabric utilizing shared memory. In: 9th EUROMICRO Conference on Digital System Design, Croatia, August 2006, pp. 180–188 (2006)
Mhamdi, L., Kachris, C., Vassiliadis, S.: A reconfigurable hardware based embedded scheduler for buffered crossbar switches. In: 14th ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, CA, February 2006, pp. 143–149 (2006)
Papaefstathiou, I., Kornaros, G., Chrysos, N.: Using Buffered crossbars for chip interconnection. In: 17th Great Lakes Symposium on VLSI, Stresa-Lago Maggiore, Italy, March 2007, pp. 90–95 (2007)
Yoshigoe, K., Christensen, K., Jacob, A.: The RR/RR CICQ switch: hardware design for 10-Gbps link speed. In: 22nd IEEE International Performance, Computing, and Communications Conference, Phoenix, AZ, April 2003, pp. 481–485 (2003)
He, S., et al.: On Guaranteed Smooth Switching for Buffered Crossbar Switches. IEEE/ACM Transactions on Networking 16(3), 718–731 (2008)
Magill, B., Rohrs, C., Stevenson, R.: Output-queued switch emulation by fabrics with limited memory. IEEE Journal on Selected Areas in Communications 21(4), 606–615 (2003)
Mhamdi, L., Hamdi, M.: Output queued switch emulation by a one-cell-internally buffered crossbar switch. In: IEEE GLOBECOM 2003, San Francisco, CA (December 2003)
Stephens, D., Zhang, H.: Implementing distributed packet fair queueing in a scalable switch architecture. In: IEEE INFOCOM 1998, San Francisco, CA (March 1998)
Chuang, S., Iyer, S., McKeown, N.: Practical algorithms for performance guarantees in buffered crossbars. In: IEEE INFOCOM 2005, Miami, FL (March 2005)
Pan, D., Yang, Y.: Providing flow based performance guarantees for buffered crossbar switches. In: IEEE IPDPS 2008, Miami, FL (April 2008)
Turner, J.: Strong performance guarantees for asynchronous crossbar schedulers. IEEE/ACM Transactions on Networking (to appear, 2009)
Rojas-Cessa, R., Oki, E., Jing, Z., Chao, H.: CIXB-1: Combined input-once-cell-crosspoint buffered switch. In: IEEE HPSR 2001, Dallas, TX (July 2001)
Rojas-Cessa, R., Oki, E., Chao, H.: CIXOB-k: Combined input-crosspoint-output buffered packet switch. In: IEEE Globecom 2001, San Antonio, TX (November 2001)
Mhamdi, L., Hamdi, M.: MCBF: a high-performance scheduling algorithm for buffered crossbar switches. IEEE Communications Letters 7(9), 451–453 (2003)
Zhang, X., Bhuyan, L.: An efficient scheduling algorithm for combined-input-crosspoint-queued (CICQ) switches. In: IEEE Globecom 2004, Dallas, TX (November 2004)
Katevenis, M., Passas, G., Simos, D., Papaefstathiou, I., Chrysos, N.: Variable packet size buffered crossbar (CICQ) switches. In: Proc. IEEE ICC 2004, Paris, France (June 2004)
Pan, D., Yang, Y.: Localized independent packet scheduling for buffered crossbar switches. IEEE Transactions on Computers 58(2), 260–274 (2009)
Parekh, A., Gallager, R.: A generalized processor sharing approach to flow control in integrated services networks: the single node case. IEEE/ACM Trans. Networking 1(3), 344–357 (1993)
Pan, D., Yang, Y.: Max-min fair bandwidth allocation algorithms for packet switches. In: IEEE IPDPS 2007, Long Beach, CA (March 2007)
Hosaagrahara, M., Sethu, H.: Max-min fairness in input-queued switches. IEEE Transactions on Parallel and Distributed Systems 19(4), 462–475 (2008)
McKeown, N., Mekkittikul, A., Anantharam, V., Walrand, J.: Achieving 100% throughput in an input queued switch. IEEE Trans. Commun. 47(8), 1260–1267 (1999)
Bennett, J., Zhang, H.: WF2Q: worst-case fair weighted fair queueing. In: IEEE INFOCOM 1996, San Francisco, CA (March 1996)
Leonardi, E., Mellia, M., Neri, F., Marsan, M.: On the stability of input-queued switches with speed-up. IEEE/ACM Trans. Networking 9(1), 104–118 (2001)
Farleigh, C., et al.: Packet-level traffic measurements from the Sprint IP backbone. IEEE Network 17(6), 6–16 (2003)
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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Pan, D., Yang, Z., Makki, K., Pissinou, N. (2009). Providing Performance Guarantees for Buffered Crossbar Switches without Speedup. In: Bartolini, N., Nikoletseas, S., Sinha, P., Cardellini, V., Mahanti, A. (eds) Quality of Service in Heterogeneous Networks. QShine 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 22. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-10625-5_19
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DOI: https://doi.org/10.1007/978-3-642-10625-5_19
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-10624-8
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