Abstract
The reliability of nano-sized combinational circuits can be estimated by using different techniques, such as mathematical equations, Monte Carlo simulations, algorithmic approaches, and combinations of these. Commonly used equations are functions of gate count, and of the reliability and number of devices that make up the gates. The aim of this paper is to present a(n alternative) neural-based approach which is more accurate than applying simple equations, while being faster than the time-consuming Monte Carlo technique.
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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Beg, A. (2009). Improving Nano-circuit Reliability Estimates by Using Neural Methods. In: Schmid, A., Goel, S., Wang, W., Beiu, V., Carrara, S. (eds) Nano-Net. NanoNet 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 20. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04850-0_35
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DOI: https://doi.org/10.1007/978-3-642-04850-0_35
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