Abstract
A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans.
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© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
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Xu, H., Pavlidis, V.F., De Micheli, G. (2009). Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. In: Schmid, A., Goel, S., Wang, W., Beiu, V., Carrara, S. (eds) Nano-Net. NanoNet 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 20. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04850-0_21
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DOI: https://doi.org/10.1007/978-3-642-04850-0_21
Publisher Name: Springer, Berlin, Heidelberg
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