Abstract
A new approach for inserting repeaters in 3-D interconnects is proposed. The allocation of repeaters along an interplane interconnect is iteratively determined. The proposed approach is compared with two other techniques based on conventional methods used for 2-D interconnects. Simulation results show that the proposed approach decreases the total wire delay up to 42% as compared to conventional approaches. The complexity of the proposed algorithm is linear to the number of planes that the wire spans.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
Bakoglu, H.B., Meindl, J.D.: Optimal Interconnection Circuits for VLSI. IEEE Transactions on Electron Devices 32(5), 903–909 (1985)
Dhar, S., Franklin, M.A.: Optimal Buffer Circuits for Driving Long Uniform Lines. IEEE Journal of Solid-State Circuits 26(1), 32–40 (1991)
Adler, V., Friedman, E.G.: Uniform Repeater Insertion in RC Trees. IEEE Transactions on Circuits and Systems I 47(10), 1515–1523 (2000)
Alpert, C., Devgan, A.: Wire Segmenting for Improved Buffer Insertion. In: IEEE/ACM Design Automation Conference, pp. 588–593 (1997)
Pavlidis, V.F., Friedman, E.G.: Timing-Driven Via Placement Heuristics For Three-dimensional ICs. Integration, the VLSI Journal 41(4), 489–508 (2008)
He, X., Dong, S., Ma, Y., Hong, X.: Simultaneous Buffer and Interlayer Via Planning for 3D Floorplanning. In: IEEE International Symposium on Quality Electronic Design, pp. 740–745 (2009)
Elmore, W.C.: The Transient Analysis of Damped Linear Networks with Particular Regard to Wideband Amplifiers. Journal of Applied Physics 19(1), 55–63 (1948)
Waltz, R.A., Morales, J.L., Nocedal, J., Orban, D.: An Interior Algorithm For Nonlinear Optimization that Combines Line Search and Trust Region Steps. Mathematical Programming 107(3), 391–408 (2006)
ASU Predictive Technology Model, http://www.eas.asu.edu/~ptm/
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2009 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering
About this paper
Cite this paper
Xu, H., Pavlidis, V.F., De Micheli, G. (2009). Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits. In: Schmid, A., Goel, S., Wang, W., Beiu, V., Carrara, S. (eds) Nano-Net. NanoNet 2009. Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering, vol 20. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04850-0_21
Download citation
DOI: https://doi.org/10.1007/978-3-642-04850-0_21
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-04849-4
Online ISBN: 978-3-642-04850-0
eBook Packages: Computer ScienceComputer Science (R0)