Abstract
The chapter introduces such basic topics, as principles of microprogram control and specification of the control unit behavior using the graph-scheme of algorithm. Next, some methods of control algorithm interpretation, such as finite-state machines (FSM) and microprogram control units (MCU), are discussed. Last part of the chapter is devoted to the organization principles of compositional microprogram control units, which can be viewed as compositions of finite-state machine and microprogram control unit. These control units provide efficient interpretation of the so-called linear GSA, in which long sequences of operator vertices can be found. These sequences are called operational linear chains (OLC). Microinstructions corresponding to the components of OLC are addressed using the principle of natural microinstruction addressing. It permits to use the counter to keep microinstruction addresses and to simplify the combinational part of control unit, as compared with the classical Moore FSM. The Mealy FSM is used in CMCU to address microinstructions. It permits to calculate the transition address during one cycle of control unit’s operation. Due to this feature, performance of the CMCU (proportional to the number of cycles needed to execute the control algorithm) is better than performance of the equivalent MCU with natural microinstruction addressing.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Adamski, M., Barkalov, A.: Architectural and Sequential Synthesis of Digital Devices. University of Zielona GĂ³ra Press, Zielona GĂ³ra (2006)
Agerwala, T.: Microprogram optimization: A survey. IEEE Transactions of Computers (10), 962–973 (1976)
Agrawala, A., Rauscher, T.: Foundations of Microprogramming. Academic Press, New York (1976)
Amann, R., Baitinger, U.: Optimal state chains and states codes in finite state machines. IEEE Transactions on Computer-Aided Design 8(2), 153–170 (1989)
Anceau, F.: The Architecture of Microprocessors. Addison-Wesley, Workingham (1986)
Asahar, P., Devidas, S., Newton, A.: Sequential Logic Synthesis. Kluwer Academic Publishers, Boston (1992)
Bacchetta, P., Daldos, L., Sciuto, D., Silvano, C.: Low-power state assignment techniques for finite state machines. In: Proc. of the IEEE Inter. Symp. on Circuits and Systems (ISCAS 2000), vol. 2, pp. 641–644 (2000)
Baranov, S.: Logic and System Design of Digital Systems. TUT Press, Tallinn (2008)
Baranov, S.I.: Logic Synthesis of Control Automata. Kluwer Academic Publishers, Dordrecht (1994)
Barkalov, A., Salomatin, V., Starodubov, K., Das, K.: Optimization of mealy automaton logic using programmable logic arrays. Cybernetics and system analysis 27(5), 789–793 (1991)
Barkalov, A., Titarenko, L.: Logic Synthesis for Compositional Microprogram Control Units. Springer, Berlin (2008)
Barkalov, A., Titarenko, L.: Synthesis of Operational and Control Automata. UNITECH, Donetsk (2009)
Barkalov, A., WÄ™grzyn, M.: Design of Control Units With Programmable Logic. University of Zielona GĂ³ra Press (2006)
Barkalov, A.A.: Principles of optimization of logic circuit of Moore FSM. Cybernetics and System Analysis (1), 65–72 (1998) (in Russian)
Barkalov, A.A.: Microprogram control unit as composition of automate with programmable and hardwired logic. Automatics and computer technique (4), 36–41 (1983) (in Russian)
Bomar, B.W.: Implementation of microprogrammed control in FPGAs. IEEE Transactions on Industrial Electronics 49(2), 415–422 (2002)
Brayton, R., Hatchel, G., McMullen, C., Sangiovanni-Vincentelli, A.: Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Boston (1984)
Brayton, R., Rudell, R., Sangiovanni-Vincentelli, A., Wang, A.: MIS: a multi- level logic optimization system. IEEE Transactions on Computer-Aided Design 6, 1062–1081 (1987)
Webb, C., Liptay, J.: A high-frequency custom cmos s/390 microprocessor. IBM Journal of research and Development 41(4/5), 463–473 (1997)
Chattopadhyay, S.: Area conscious state assignment with flip-flop and output polarity selection for finite state machines synthesis – a genetic algorithm. The Computer Journal 48(4), 443–450 (2005)
Chattopadhyay, S., Chaudhuri, P.: Genetic algorithm based approach for integrated state assignment and flipflop selection in finite state machines synthesis. In: Proc. of the IEEE Inter. Conf. on VLSI Design, pp. 522–527. IEEE Computer Society, Los Alamitos (1998)
Chu, Y.C.: Computer Organization and Microprogramming. Prentice Hall, Englewood Cliffs (1972)
Ciesielski, M., Jang, S.: PLADE: A two-stage PLA decomposition. IEEE Transactions on Computer-Aided Design 11(8) (1992)
Clements, A.: The Principles of Computer Hardware. Oxford University Press, Inc., New York (2000)
Czerwinski, R., Kania, D.: State assignment method for high speed FSM. In: Proc. of Programmable Devices and Systems, pp. 216–221 (2004)
Czerwinski, R., Kania, D.: State assignment for PAL-based CPLDs. In: Proc. of 8th Euromicro Sym. on Digital System Design, pp. 127–134 (2005)
Dasgupta, S.: The organization of microprogram stores. ACM Computing Survey (24), 101–176 (1979)
Sasao, T., Debnath, D.: Doutput phase optimization for and-or-exor plas with decoders and its application to design of adders. IFICE Transactions on Information and Systems E88-D (7), 1492–1500 (2005)
Deniziak, S., Sapiecha, K.: An efficient algorithm of perfect state encoding for CPLD based systems. In: Proceedings of IEEE Workshop on Design and Diagnostic of Electronic Circuits and Systems (DDECS 1998), pp. 47–53 (1998)
Devadas, S., Ma, H.: Easily testable PLA-based finite state machines. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 9(6), 604–611 (1990)
Devadas, S., Ma, H., Newton, A., Sangiovanni-Vincentelli, A.: MUSTANG: State assignment of finite state machines targeting multilevel logic implementation. IEEE Transactions on Computer-Aided Design 7(12), 1290–1300 (1988)
Devadas, S., Newton, A.: Exact algorithms for output encoding, state assignment, and four-level boolean minimization. IEEE Transactions on Computer-Aided Design 10(1), 143–154 (1991)
Du, X., Hachtel, G., Lin, B., Newton, A.: MUSE: a multilevel symbolic encoding algorithm for state assignment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 10(1), 28–38 (1991)
Escherman, B.: State assignment for hardwired vlsi control units. ACM Computing Surveys 25(4), 415–436 (1993)
Gajski, D.: Principles of Digital Design. Prentice Hall, New York (1997)
Goren, S., Ferguson, F.: CHESMIN: a heuristic for state reduction of incompletely specified finite state machines. In: Proc. of the Design, Automation and Test in Europe Conf. and Exhibition (DATE 2002), pp. 248–254 (2002)
Gupta, B., Narayanan, H., Desai, M.: A state assignment scheme targeting performance and area. In: Proc. of 12th Inter. Conf. on VLSI Design, pp. 378–383 (1999)
Habib, S.: Microprogramming and Firmware Engineering Methods. John Wiley and Sons, New York (1988)
Hu, H., Xue, H., Bian, J.: A heuristic state assignment algorithm targeting area. In: Proc. of 5th Inter. Conf. on ASIC, vol. 1, pp. 93–96 (2003)
Huang, J., Jou, J., Shen, W.: ALTO: An iterative area/performance algorithms for LUT-based FPGA technology mapping. IEEE Transactions on VLSI Systems 18(4), 392–400 (2000)
Husson, S.: Microprogramming: Principles and Practices. Prentice Hall, Englewood Cliffs (1970)
Iranli, A., Rezvani, P., Pedram, M.: Low power synthesis of finite state machines with mixed D and T flip-flops. In: Proc. of the Asia and South Pacific– DAC, pp. 803–808 (2003)
Flynn, M.J., Rosin, R.F.: Microprogramming: An introduction and a viewpoint. IEEE transactions on Computers C–20(7), 727–731 (1971)
Kubatova, H.: Finie State Machine Implementation in FPGAs. In: Software Frameworks and Embedded Control Systems, pp. 177–187. Springer, New York (2005)
Maxfield, C.: The Design Warrior’s Guide to FPGAs. Academic Press, Inc., Orlando (2004)
De Micheli, G.: Symbolic design of combinational and sequential logic implemented by two–level macros. IEEE Transactions on Computer-Aided Design 5(9), 597–616 (1986)
De Micheli, G.: Synthesis and Optimization of Digital Circuits. McGraw-Hill, New York (1994)
Minns, P., Elliot, I.: FSM-based digital design using Verilog HDL. John Wiley and Sons, Chichester (2008)
Papachristou, C.: Hardware microcontrol schemes using PLAs. In: Proceeding of 14th Microprogramming Workshop, vol. 2, pp. 3–15 (1981)
Papachristou, C., Gambhir, S.: A microsequencer architecture with firmware support for modular microprogramming. ACM SIGMICRO Newsletters 13(4) (1982)
Park, S., Yang, S., Cho, S.: Optimal state assignment technique for partial scan designs. Electronic Letters 36(18), 1527–1529 (2000)
Patterson, D., Henessy, J.: Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann, San Moteo (1998)
Pedram, C., Despain, A.: Low-power state assignment targeting two- and multilevel logic implementations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 17(12), 1281–1291 (1998)
Pomerancz, I., Cheng, K.: STOIC: state assignment based on output/input functions. IEEE Transactions on Computer-Aided Design of Integrated Circuits and System 12(8), 1123–1131 (1993)
Pugh, E., Johnson, L., Palmer, J.: IBM’s 360 and Early 370 Systems. MIT Press, Cambridge (1991)
Rho, J., Hatchel, F., Somenzi, R., Jacoby, R.: Exact and heuristic algorithms for the minimization of incompletely specified state machines. IEEE Transactions on Computer-Aided Design 13(2), 167–177 (1994)
Rudell, R., Sangiovanni-Vincentelli, A.: Multiple-valued minimization for pla optimization. IEEE Transactions on Computer-Aided Design 6(5), 727–750 (1987)
Salisbury, A.: Microprogrammable Computer Architectures. Am Elstein, New York (1976)
Sasao, T.: Input variable assignment and output phase optimization of pla optimization. IEEE Transactions on Computers 33(10), 879–894 (1984)
Smith, M.: Application-Specific Integrated Circuits. Addison-Wesley, Boston (1997)
Solovjev, V., Czyzy, M.: Refined CPLD macrocells architecture for effective FSM implementation. In: Proc. of the 25th EUROMICRO Conference, Milan, Italy, vol. 1, pp. 102–109 (1999)
Solovjev, V., Czyzy, M.: The universal algorithm for fitting targeted unit to complex programmable logic devices. In: Proc. of the 25th EUROMICRO Conference, Milan, Italy, vol. 1, pp. 286–289 (1999)
Solovjev, V.V.: Design of Digital Systems Using the Programmable Logic Integrated Circuits. In: Hot line – Telecom, Moscow (2001) (in Russian)
Tucker, S.: Microprogram control for system/360. IBM System Journal 6(4), 222–241 (1967)
Venkatamaran, G., Reddy, S., Pomerancz, I.: GALLOP: genetic algorithm based low power fsm synthesis by simultaneous partitioning and state assignment. In: Proc. of 16th Inter. Conf. on VLSI Design, pp. 533–538 (2003)
Villa, T., Saldachna, T., Brayton, R., Sangiovanni-Vincentelli, A.: Symbolic two-level minimization. IEEE Transactions on Computer-Aided Design 16(7), 692–708 (1997)
Villa, T., Sangiovanni-Vincentelli, A.: NOVA: State assignment of finite state machines for optimal two-level logic implementation. IEEE Transactions on Computer-Aided Design 9(9), 905–924 (1990)
Wilkes, M.: The best way to design an automatic calculating machine. In: Proc. of Manchester University Computer Inaugural Conference (1951)
Wilkes, M., Stringer, J.: Microprogramming and the design of the control circuits in an electronic digital computer. In: Proc. of Cambridge Philosophical Society, vol. 49, pp. 230–238 (1953)
Xia, Y., Almani, A.: Genetic algorithm based state assignment for power and area optimization. In: IEEE Proc. on Computers and Digital Techniques, vol. 149, pp. 128–133 (2002)
Rights and permissions
Copyright information
© 2009 Springer-Verlag Berlin Heidelberg
About this chapter
Cite this chapter
Barkalov, A., Titarenko, L. (2009). Hardwired Interpretation of Control Algorithms. In: Logic Synthesis for FSM-Based Control Units. Lecture Notes in Electrical Engineering, vol 53. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-04309-3_1
Download citation
DOI: https://doi.org/10.1007/978-3-642-04309-3_1
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-04308-6
Online ISBN: 978-3-642-04309-3
eBook Packages: EngineeringEngineering (R0)