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Area Chip Consumption by a Novel Digital CNN Architecture for Pattern Recognition

  • Emil Raschman
  • Daniela Ďuračková
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5768)

Abstract

The implementation for the digital neural networks on a chip requires a lot of chip area consumption. Our contribution paper deals therefore with the design of a novel type of digital CNN architecture focused on pattern recognition application. The novel designed network we compare with another two CNN implementation of digital network on a chip used for pattern recognition by the selected parameters as the speed and chip area consumption. From the comparison we can recognize that our proposed digital CNN network is the best from the other ones.

Keywords

CNN pattern recognition digital implementation of CNN networks 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2009

Authors and Affiliations

  • Emil Raschman
    • 1
  • Daniela Ďuračková
    • 1
  1. 1.Faculty of Electrical Engineering and Information TechnologySlovak University of TechnologyBratislavaSlovakia

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