Design and Implementation of High Performance Viterbi Decoder for Mobile Communication Data Security
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With the ever increasing growth of data communication in the field of e-commerce transactions and mobile communication data security has gained utmost importance. However the conflicting requirements of power, area and throughput of such applications make hardware cryptography an ideal choice. Dedicated hardware devices such as FPGAs can run encryption routines concurrently with the host computer which runs other applications. The use of error correcting code has proven to be are effective way to overcome data corruption in digital communication channel. In this paper, we describe the design and implementation of a reduced complexity decode approach along with minimum power dissipation FPGAs for Mobile Communication data security.
KeywordsData security FPGA Hardware Cryptography Viterbi algorithm
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