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Programmable Accelerators for Reconfigurable Video Decoder

  • Tero Rintaluoma
  • Timo Reinikka
  • Joona Rouvinen
  • Jani Boutellier
  • Pekka Jääskeläinen
  • Olli Silvén
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5657)

Abstract

Practically all modern video coding standards such as H.264, MPEG-4 and VC-1 are based on hybrid transform based block motion compensated techniques, that employ almost the same coding tools. The same approach is used with numerous non-standard proprietary codecs, with decoders available via Internet as browser plugins. For mobile devices power efficient hardware accelerators have been developed, but usually only a few standards are supported. Consequently, the decoding of the other formats, including the non-standard ones is done by software, sacrificing the battery life. In this paper we present programmable accelerators for arithmetic code decoding and motion compensation, that can be used with multiple video standards. These functions consume more than half of the cycles in software based decoders. Although the accelerators were originally designed for H.264 standard, they are rather generic for the respective coding tools. They have been implemented on application specific processor technology for flexibility and energy efficiency with the aim of achieving the performance needed for decoding high definition (1920x1088, 30 fps) video.

Keywords

Video Code Motion Compensation Intra Prediction Hardware Accelerator Video Decoder 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    ISO/IEC 14496-2:2004: Information technology - Coding of audio-visual objects - Part 2: Visual. ISO/IEC. Third edn. (June 2004)Google Scholar
  2. 2.
    ISO/IEC 14496-10:2005; Recommendation ITU-T H.264: SERIES H: AUDIOVISUAL AND MULTIMEDIA SYSTEMS Infrastructure of audiovisual services - Coding of moving: Advanced video coding for generic audiovisual services video. ITU-T (November 2005)Google Scholar
  3. 3.
    Fitzek, F.H.P., Reichert, F.: Mobile Phone Programming: and its Application to Wireless Networking. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  4. 4.
    SMPTE 421M-2006: VC-1 Compressed Video Bitstream Format and Decoding Process. SMPTE (February 2006)Google Scholar
  5. 5.
    Jer-Min, H., Chun-Jen, T.: Analysis of an soc architecture for mpeg reconfigurable video coding framework. In: IEEE International Symposium on Circuits and Systems, ISCAS 2007, May 27-30, pp. 761–764 (2007)Google Scholar
  6. 6.
    Eeckhaut, H., Christiaens, M., Stroobandt, D., Nollet, V.: Optimizing the critical loop in the h.264/avc cabac decoder. In: IEEE International Conference on Field Programmable Technology, FPT 2006, December 2006, pp. 113–118 (2006)Google Scholar
  7. 7.
    Jääskeläinen, P., Guzma, V., Cilio, A., Pitkänen, T., Takala, J.: Codesign toolset for application-specific instruction-set processors, vol. 6507. SPIE (2007) 65070XGoogle Scholar
  8. 8.
    On2 Technologies (2008), http://www.on2.com
  9. 9.
    ISO/IEC JTC1/SC29/WG11 N8069: Reconfigurable Video Coding Requirements v.2.0. ISO/IEC (November 2006)Google Scholar
  10. 10.
    Richardson, I., Bystrom, M., Kannangara, S., Frutos, D.: Dynamic configuration: Beyond video coding standards. In: IEEE System on Chip Conference. IEEE, Los Alamitos (2008)Google Scholar
  11. 11.
    Lucarz, C., Mattavelli, M., Thomas-Kerr, J., Janneck, J.: Reconfigurable media coding: A new specification model for multimedia coders. In: IEEE Workshop on Signal Processing Systems, October 2007, pp. 481–486 (2007)Google Scholar
  12. 12.
    Wang, S.Z., Lin, T.A., Liu, T.M., Lee, C.Y.: A new motion compensation design for h.264/avc decoder. In: IEEE International Symposium on Circuits and Systems, ISCAS 2005, May 2005, vol. 5, pp. 4558–4561 (2005)Google Scholar
  13. 13.
    Tsai, C.Y., Chen, T.C., Chen, T.W., Chen, L.G.: Bandwidth optimized motion compensation hardware design for h.264/avc hdtv decoder. In: 48th Midwest Symposium on Circuits and Systems, August 2005, vol. 2, pp. 1199–1202 (2005)Google Scholar
  14. 14.
    Zatt, B., Ferreira, V., Agostini, L.V., Wagner, F.R., Susin, A.A., Bampi, S.: Motion compensation hardware accelerator architecture for h.264/avc. In: Mery, D., Rueda, L. (eds.) PSIVT 2007. LNCS, vol. 4872, pp. 24–35. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  15. 15.
    Li, Y., He, Y.: Bandwidth optimized and high performance interpolation architecture in motion compensation for h.264/avc hdtv decoder. J. Signal Process. Syst. 52(2), 111–126 (2008)CrossRefGoogle Scholar
  16. 16.
    Marpe, D., Schwarz, H., Wiegand, T.: Context-based adaptive binary arithmetic coding in the h.264/avc video compression standard. IEEE Transactions on Circuits and Systems for Video Technology 13(7), 620–636 (2003)CrossRefGoogle Scholar
  17. 17.
    On2 Technologies (2008), http://www.on2.com
  18. 18.

Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Tero Rintaluoma
    • 1
  • Timo Reinikka
    • 2
  • Joona Rouvinen
    • 4
  • Jani Boutellier
    • 2
  • Pekka Jääskeläinen
    • 3
  • Olli Silvén
    • 2
  1. 1.On2 TechnologiesOuluFinland
  2. 2.Department of Electrical and Information EngineeringUniversity of OuluFinland
  3. 3.Tampere University of TechnologyTampereFinland
  4. 4.Valmet Automotive, UusikaupunkiFinland

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