Abstract
Instruction-Set Extensions (ISEs) have gained prominence in the past few years as a useful method for tailoring the ISAs (Instruction-Set Architectures) of ASIPs (Application Specific Instruction-Set Processors) to the computational requirements of various embedded applications. This work presents a generic and easily adaptable flow for application oriented ISE design that supports both of the prevalent ASIP design paradigms - complete ISA design from scratch through an extensive design-space exploration, or limited ISA adaptation for a pre-designed and pre-verified base-processor core. The broad applicability of this design flow is demonstrated using ISA customization case studies for both of these two design philosophies.
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© 2009 IFIP International Federation for Information Processing
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Karuri, K., Leupers, R., Ascheid, G., Meyr, H. (2009). A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs). In: Bertels, K., Dimopoulos, N., Silvano, C., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2009. Lecture Notes in Computer Science, vol 5657. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03138-0_22
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DOI: https://doi.org/10.1007/978-3-642-03138-0_22
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-642-03137-3
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