A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)

  • Kingshuk Karuri
  • Rainer Leupers
  • Gerd Ascheid
  • Heinrich Meyr
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5657)


Instruction-Set Extensions (ISEs) have gained prominence in the past few years as a useful method for tailoring the ISAs (Instruction-Set Architectures) of ASIPs (Application Specific Instruction-Set Processors) to the computational requirements of various embedded applications. This work presents a generic and easily adaptable flow for application oriented ISE design that supports both of the prevalent ASIP design paradigms - complete ISA design from scratch through an extensive design-space exploration, or limited ISA adaptation for a pre-designed and pre-verified base-processor core. The broad applicability of this design flow is demonstrated using ISA customization case studies for both of these two design philosophies.


Target Application Design Space Exploration Data Flow Graph Schedule Level Processor Model 
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Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Kingshuk Karuri
    • 1
  • Rainer Leupers
    • 1
  • Gerd Ascheid
    • 1
  • Heinrich Meyr
    • 1
  1. 1.Institute for Integrated Signal Processing SystemsRWTH Aachen UniversityAachenGermany

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