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Programmable and Scalable Architecture for Graphics Processing Units

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Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS 2009)

Part of the book series: Lecture Notes in Computer Science ((LNTCS,volume 5657))

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Abstract

Graphics processing is an application area with high level of parallelism at the data level and at the task level. Therefore, graphics processing units (GPU) are often implemented as multiprocessing systems with high performance floating point processing and application specific hardware stages for maximizing the graphics throughput.

In this paper we evaluate the suitability of Transport Triggered Architectures (TTA) as a basis for implementing GPUs. TTA improves scalability over the traditional VLIW-style architectures making it interesting for computationally intensive applications. We show that TTA provides high floating point processing performance while allowing more programming freedom than vector processors.

Finally, one of the main features of the presented TTA-based GPU design is its fully programmable architecture making it suitable target for general purpose computing on GPU APIs which have become popular in recent years.

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Author information

Authors and Affiliations

  1. Department of Computer Architecture, Computer Science and Artificial Intelligence, Universidad Rey Juan Carlos, C/ Tulipán s/n, 28933 Móstoles, Madrid, Spain

    Carlos S. de La Lama

  2. Department of Computer Systems, Tampere University of Technology, Korkeakoulunkatu 10, 33720, Tampere, Finland

    Pekka Jääskeläinen & Jarmo Takala

Authors
  1. Carlos S. de La Lama
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  2. Pekka Jääskeläinen
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  3. Jarmo Takala
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Editor information

Editors and Affiliations

  1. Delft University of Technology, Mekelweg 4, 2628, Delft, CD, The Netherlands

    Koen Bertels  & Stephan Wong  & 

  2. Department of Electrical and Computer Engineering, University of Victoria, P.O. Box 3055, V8W 3P6, Victoria, BC, Canada

    Nikitas Dimopoulos

  3. Dipartimento di Elettronica e Informazione, Politecnico di Milano, P.za Leonardo Da Vinci 32, 20133, Milan, Italy

    Cristina Silvano

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© 2009 IFIP International Federation for Information Processing

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de La Lama, C.S., Jääskeläinen, P., Takala, J. (2009). Programmable and Scalable Architecture for Graphics Processing Units. In: Bertels, K., Dimopoulos, N., Silvano, C., Wong, S. (eds) Embedded Computer Systems: Architectures, Modeling, and Simulation. SAMOS 2009. Lecture Notes in Computer Science, vol 5657. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-03138-0_2

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  • DOI: https://doi.org/10.1007/978-3-642-03138-0_2

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-642-03137-3

  • Online ISBN: 978-3-642-03138-0

  • eBook Packages: Computer ScienceComputer Science (R0)

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