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Prediction in Dynamic SDRAM Controller Policies

  • Ying Xu
  • Aabhas S. Agarwal
  • Brian T. Davis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5657)

Abstract

Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution time can be reduced by using a state machine which predicts, for each access, the policy which will minimize latency. Two-level dynamic predictors are incorporated into the SDRAM controller. A range of organizations for dynamic predictors are described, and the performance improvements predicted by simulation are compared using execution time and prediction accuracy as metrics. Results show that predictive SDRAM controllers, reduce execution time by 1.6% to 17% over static access control policies. The prediction accuracy of the best predictor results in 93% prediction accuracy, with 87% accuracy for OP state preferred accesses, and 96% for CPA state preferred accesses. Results show that execution time is strongly correlated to the prediction accuracy of OP, suggesting directions for future predictor development.

Keywords

SDRAM Memory Latency Access Control Policy 

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References

  1. 1.
    Burger, D., Austin, T.M.: The SimpleScalar Tool Set, Version 2.0., SimpleScalar LLCGoogle Scholar
  2. 2.
    Citron, D.: MisSPECCulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences. In: Proceedings of ISCA-30, pp. 52–61 (2003)Google Scholar
  3. 3.
    Hamilton, S.: Taking Moore’s Law into the Next Century. Computer 32(1), 43–48 (1999)CrossRefGoogle Scholar
  4. 4.
    Hur, I., Lin, C.: Adaptive History-Based Memory Schedulers. In: Proceedings of MICRO 37, pp. 343–354 (2004)Google Scholar
  5. 5.
    Ma, C., Chen, S.: A DRAM Precharge Policy Based on Address Analysis. In: Proceedings of DSD, pp. 244–248 (2007)Google Scholar
  6. 6.
    Rixner, S., Dally, W.J., Kappasi, U.J., Mattson, P., Ownes, J.D.: Memory Access Scheduling. In: Proceedings of ISCA-27, pp. 128–138 (2000)Google Scholar
  7. 7.
    Skadron, K., Clark, D.W.: Design Issues and Tradeoffs for Write Buffers. In: Proceedings of HPCA-3, pp. 44–155 (1997)Google Scholar
  8. 8.
    SPEC CPU 2000V1.2, Standard Performance Evaluation Corporation (December 2001)Google Scholar
  9. 9.
    Stankovic, V., Milenkovic, N.: DRAM Controller with a Complete Predictor: Preliminary Results. In: Proceedings of TELSKS, pp. 593–596 (2005)Google Scholar
  10. 10.
    Wong, A.: Breaking through the BIOS Barrier: the Definitive BIOS Optimization Guide for PCs. Prentice Hall, Englewood Cliffs (2004)Google Scholar
  11. 11.
    Xu, Y.: Prediction in Dynamic SDRAM Controller Policy, MSEE Thesis, College of Engineering, Michigan Tech. (2006)Google Scholar
  12. 12.
    Yeh, T., Patt, Y.N.: A Comparison of Dynamic Branch Predictors that Use Two Levels of Branch History. In: Proceedings of ISCA-20, pp. 257–266 (1993)Google Scholar

Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Ying Xu
    • 1
  • Aabhas S. Agarwal
    • 1
  • Brian T. Davis
    • 1
  1. 1.Department of Electrical and Computer Engineering and School of TechnologyMichigan Technological UniversityHoughton

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