Prediction in Dynamic SDRAM Controller Policies

  • Ying Xu
  • Aabhas S. Agarwal
  • Brian T. Davis
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5657)


Memory access latency can limit microcontroller system performance. SDRAM access control policies impact latency through SDRAM device state. It is shown that execution time can be reduced by using a state machine which predicts, for each access, the policy which will minimize latency. Two-level dynamic predictors are incorporated into the SDRAM controller. A range of organizations for dynamic predictors are described, and the performance improvements predicted by simulation are compared using execution time and prediction accuracy as metrics. Results show that predictive SDRAM controllers, reduce execution time by 1.6% to 17% over static access control policies. The prediction accuracy of the best predictor results in 93% prediction accuracy, with 87% accuracy for OP state preferred accesses, and 96% for CPA state preferred accesses. Results show that execution time is strongly correlated to the prediction accuracy of OP, suggesting directions for future predictor development.


SDRAM Memory Latency Access Control Policy 


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Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Ying Xu
    • 1
  • Aabhas S. Agarwal
    • 1
  • Brian T. Davis
    • 1
  1. 1.Department of Electrical and Computer Engineering and School of TechnologyMichigan Technological UniversityHoughton

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