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Towards Automated FSMD Partitioning for Low Power Using Simulated Annealing

  • Nainesh Agarwal
  • Nikitas J. Dimopoulos
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5657)

Abstract

We propose a technique to efficiently partition a FSMD (Finite State Machine with Datapath) using a simulated annealing approach. The FSMD is split into two or more simpler communicating processors. These separate processors can then be clock gated or power gated to achieve dramatic power savings since only one processor is active at any given time. We develop a framework to estimate the potential power savings from partitioning. Using several sample circuits, the estimation framework shows that when the original machine is partitioned into two submachines, on average, 32% static power savings and 19% dynamic power savings can be expected, with a performance impact of 2%. The power savings with more than two partitions can be even higher, with a larger performance impact.

Keywords

Simulated Annealing Finite State Machine Simulated Annealing Algorithm Power Saving Sequential Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Nainesh Agarwal
    • 1
  • Nikitas J. Dimopoulos
    • 1
  1. 1.Department of Electrical and Computer EngineeringUniversity of VictoriaVictoriaCanada

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