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Implementation of W-CDMA Cell Search on a FPGA Based Multi-Processor System-on-Chip with Power Management

  • Roberto Airoldi
  • Fabio Garzia
  • Tapani Ahonen
  • Dragomir Milojevic
  • Jari Nurmi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5657)

Abstract

In this paper we describe a general purpose, homogeneous Multi-Processor System-on-Chip (MPSoC) based on 9 processing clusters using COFFEE RISC processors and a hierarchical Network-on-Chip implemented on an FPGA device. The MPSoC platform integrates a cluster clock gating technique, enabling independent core and memory sleep modes. Low cluster turn-on delay allows frequent use of such technique, resulting in power savings. In order to quantify the performance of the proposed platform and the reduction of power consumption, we implement Target Cell Search part of the WCDMA, a well known SDR application. We show that the proposed MPSoC platform achieves an important speed-up (7.3X) when compared to comparable single processor platform. We also show that a significant reduction in dynamic power consumption can be achieved (50% for the complete application) using the proposed cluster clock-gating technique.

Keywords

Task Graph FPGA Device Frame Synchronization Dynamic Power Consumption Coffee Machine 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© IFIP International Federation for Information Processing 2009

Authors and Affiliations

  • Roberto Airoldi
    • 1
  • Fabio Garzia
    • 1
  • Tapani Ahonen
    • 1
  • Dragomir Milojevic
    • 2
  • Jari Nurmi
    • 1
  1. 1.Department of Computer SystemsTampere University of TechnologyTampereFinland
  2. 2.Bio, Electro and Mechanical SystemsUniversité Libre de BruxellesBrusselsBelgium

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